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公开(公告)号：US11516012B2
公开(公告)日：2022-11-29
申请号：US17144216
申请日：2021-01-08
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Sudhir K. Satpathy , Manoj R. Sastry
Abstract: In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
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公开(公告)号：US10924276B2
公开(公告)日：2021-02-16
申请号：US15982278
申请日：2018-05-17
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Sudhir K. Satpathy , Manoj R. Sastry
Abstract: In one embodiment, an apparatus includes: a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include: a multiplier circuit comprising a parallel combinatorial multiplier; and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
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公开(公告)号：US10911063B2
公开(公告)日：2021-02-02
申请号：US16592465
申请日：2019-10-03
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Examples herein relate to decoding tokens using speculative decoding operations to decode tokens at an offset from a token decoded by a sequential decoding operation. At a checkpoint, a determination is made as to whether tokens to be decoded by the sequential and speculative decoding operations align. If there is alignment, the speculatively decoded tokens after a discard window are committed and made available for access. If there is not alignment, the speculatively decoded tokens are discarded. A miss in alignment and a fullness level of a buffer that stores speculatively decoded tokens are assessed to determine a next offset level for a start of speculative decoding. A size of a discard window can be set using a relationship based on the offset level to improve buffer utilization and to attempt to improve changes of alignments.
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公开(公告)号：US10579339B2
公开(公告)日：2020-03-03
申请号：US15479424
申请日：2017-04-05
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Mathew , Sudhir K. Satpathy
Abstract: An apparatus is described. The apparatus includes a plurality of physically unclonable circuits. The apparatus includes circuitry to detect which ones of the physically unclonable circuits are unstable. The apparatus also includes circuitry to couple the unstable physically unclonable circuits to a random number generator circuit.
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公开(公告)号：US10530588B2
公开(公告)日：2020-01-07
申请号：US15382362
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sanu K. Mathew , Sudhir K. Satpathy
IPC: H04L9/32
Abstract: An apparatus is provided which comprises: a first stage of physically unclonable function (PUF) circuits to receive an n-bit challenge, wherein the first stage of PUF circuits comprise a subset of ‘n’ PUF cells each of which is to generate an output bit; and a first stage of cipher blocks to receive the output bits from the subset of ‘n’ PUF cells, wherein the first stage of cipher blocks is to generate a plurality of bits.
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Patent Agency Ranking
公开(公告)号：US20190363733A1
公开(公告)日：2019-11-28
申请号：US16402845
申请日：2019-05-03
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号：US10177782B2
公开(公告)日：2019-01-08
申请号：US14757854
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , James D. Guilford , Sanu K. Mathew , Vinodh Gopal , Vikram B. Suresh
Abstract: Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.
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公开(公告)号：US20190004770A1
公开(公告)日：2019-01-03
申请号：US15637453
申请日：2017-06-29
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Raghavan Kumar , Arvind Singh , Vikram B. Suresh , Sanu K. Mathew
Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a point multiply operation to be performed by the multiplier circuit, wherein the point multiply operation comprises point multiplication of a first plurality of operands; identify a point add operation associated with the point multiply operation, wherein the point add operation comprises point addition of a second plurality of operands, wherein the second plurality of operands comprises a first point and a second point, and wherein the first point and the second point are associated with a first coordinate system; convert the second point from the first coordinate system to a second coordinate system; perform the point add operation based on the first point associated with the first coordinate system and the second point associated with the second coordinate system; and perform the point multiply operation based on a result of the point add operation.
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公开(公告)号：US20180364982A1
公开(公告)日：2018-12-20
申请号：US15627526
申请日：2017-06-20
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh , Raghavan Kumar
Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a plurality of partial products associated with a multiply operation; partition the plurality of partial products into a first set of partial products, a second set of partial products, and a third set of partial products; determine whether the multiply operation is associated with a square operation; upon a determination that the multiply operation is associated with the square operation, compute a result based on the first set of partial products and the third set of partial products; and upon a determination that the multiply operation is not associated with the square operation, compute the result based on the first set of partial products, the second set of partial products, and the third set of partial products.
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公开(公告)号：US20180143913A1
公开(公告)日：2018-05-24
申请号：US15873729
申请日：2018-01-17
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh
CPC classification number: G06F12/1408 , G06F21/00 , G06F21/72 , G06F2212/1052 , G09C1/00 , H04L9/0631 , H04L9/3093 , H04L2209/12 , H04L2209/24
Abstract: A cryptographic hardware accelerator identifies a mapped input bit sequence by applying a mapping transformation to an input bit sequence retrieved from memory and represented by a first element of a finite-prime field. The mapped input bit sequence is represented by a first element of a composite field. The accelerator identifies a mapped first key by applying the mapping transformation to an input key represented by a second element of the finite-prime field. The mapped first key is represented by the second element. The accelerator performs, within the composite field, a cryptographic round on the mapped input bit sequence using the mapped first key during a first round of the at least one cryptographic round, to generate a processed bit sequence. The accelerator identifies an output bit sequence to be stored back in the finite-prime field by applying an inverse mapping transformation to the processed bit sequence.
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