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公开(公告)号：US11126663B2
公开(公告)日：2021-09-21
申请号：US15604793
申请日：2017-05-25
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Vikram B. Suresh , Sanu K. Mathew , Vinodh Gopal
IPC: G06F16/903 , G06F16/901 , G06F12/02
Abstract: In one embodiment, an apparatus comprises a decompression engine to determine a plurality of tokens used to encode a block of data; populate a lookup table with at least two of the tokens in order of increasing token length; disable a first portion of the lookup table and enable a second portion of the lookup table based on a value of a payload of the block of data; and search for a match between a token and the payload in the second portion of the lookup table.
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公开(公告)号：US20210211139A1
公开(公告)日：2021-07-08
申请号：US16996012
申请日：2020-08-18
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号：US20210126786A1
公开(公告)日：2021-04-29
申请号：US17144216
申请日：2021-01-08
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Sudhir K. Satpathy , Manoj R. Sastry
Abstract: In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
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公开(公告)号：US20180375527A1
公开(公告)日：2018-12-27
申请号：US15875836
申请日：2018-01-19
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
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公开(公告)号：US09965248B2
公开(公告)日：2018-05-08
申请号：US15296139
申请日：2016-10-18
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
CPC classification number: G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20180006807A1
公开(公告)日：2018-01-04
申请号：US15196686
申请日：2016-06-29
Applicant: Intel Corporation
Inventor： Vikram B. Suresh , Sudhir K. Satpathy , Sanu K. Mathew
IPC: H04L9/06
CPC classification number: H04L9/0643 , H04L9/0618 , H04L2209/20 , H04L2209/30 , H04L2209/38 , H04L2209/56
Abstract: A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor.
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7.发明授权公开(公告)号：US09806719B1
公开(公告)日：2017-10-31
申请号：US15280783
申请日：2016-09-29
Applicant: Intel Corporation
Inventor： Sanu K. Mathew , Sudhir K. Satpathy , Vikram B. Suresh
IPC: H03K19/00 , H03K19/177
CPC classification number: H03K19/17764 , H03K19/003 , H03K19/1776
Abstract: An apparatus is described. The apparatus includes a physically unclonable (PUF) circuit having a programmable input. The programmable input is to receive a value that caused the PUF circuit to strengthen its stability or strengthen its instability.
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公开(公告)号：US20170293572A1
公开(公告)日：2017-10-12
申请号：US15095783
申请日：2016-04-11
Applicant: Intel Corporation
Inventor： Sudhir K. Satpathy , Sanu K. Mathew , Vikram B. Suresh
CPC classification number: G06F12/1408 , G06F21/00 , G06F21/72 , G06F2212/1052 , G09C1/00 , H04L9/0631 , H04L9/3093 , H04L2209/12 , H04L2209/24
Abstract: A processing system includes a memory and a cryptographic accelerator operatively coupled to the memory. The cryptographic accelerator performs a split substitute byte operation within two paths of a cryptographic round by determining a first output from a first path by applying a mapped affine transformation to an input bit sequence represented by an element of a composite field of a finite-prime field, wherein the first output is represented by a first element of the composite field of the finite-prime field, and a second output from a second path by applying a scaled mapped affine transformation to the input bit sequence, wherein the second output is represented by a second element of the composite field and is equal to a multiple of the first output in the composite field.
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公开(公告)号：US20170141790A1
公开(公告)日：2017-05-18
申请号：US15335705
申请日：2016-10-27
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
CPC classification number: H03M7/3086 , H03M7/40 , H03M7/4037 , H03M7/6005 , H03M7/6023
Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method adjusting a first one of initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; and merging, by executing an instruction with the processor, first decoded data generated by decoding a first segment of the compressed data bitstream starting from the first adjusted starting position with second decoded data generated by decoding a second segment of the compressed data bitstream, the decoding of the second segment starting from a second position in the compressed data bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the compressed data bitstream.
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公开(公告)号：US09484954B1
公开(公告)日：2016-11-01
申请号：US14850721
申请日：2015-09-10
Applicant: Intel Corporation
Inventor： Vinodh Gopal , James D. Guilford , Sudhir K. Satpathy , Sanu K. Mathew
CPC classification number: H03M7/3086 , H03M7/40 , H03M7/4037 , H03M7/6005 , H03M7/6023
Abstract: Methods and apparatus to parallelize data decompression are disclosed. A method selects the initial starting positions in a compressed data bitstream. A first one of the initial starting positions is adjusted to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream. The decoding includes traversing the bitstream from the training position as though first data located at the training position is a valid token. The first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position is output. The first decoded data is merged with second decoded data generated by decoding a second segment of the bitstream. The decoding of the second segment starting from a second position in the bitstream is performed in parallel with the decoding of the first segment. The second segment precedes the first segment in the bitstream.
Abstract translation: 公开了并行化数据解压缩的方法和装置。 方法选择压缩数据比特流中的初始起始位置。 通过对比特流中训练位置开始的比特流进行解码来调整初始起始位置中的第一个以确定第一调整的起始位置。 解码包括从训练位置遍历比特流，就像位于训练位置的第一数据是有效的令牌一样。 输出从第一调整开始位置开始对比特流的第一段进行解码而生成的第一解码数据。 第一解码数据与通过对位流的第二段进行解码而生成的第二解码数据合并。 与第一段的解码并行地执行从比特流中的第二位置开始的第二段的解码。 第二段在比特流中的第一段之前。
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