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    APPLICATION AWARE MEMORY PATROL SCRUBBING TECHNIQUES
    11.
    发明申请
    APPLICATION AWARE MEMORY PATROL SCRUBBING TECHNIQUES 有权

    公开(公告)号：US20210318929A1

    公开(公告)日：2021-10-14

    申请号：US17356338

    申请日：2021-06-23

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM ,  Marcos E. CARRANZA

    IPC: G06F11/10 ,  G06F9/50 ,  G06F9/455 ,  G06F12/02

    Abstract: Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and/or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and/or predefined patterns.

    VECTOR CACHE LINE WRITE BACK PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    15.
    发明申请
    VECTOR CACHE LINE WRITE BACK PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：US20180260325A1

    公开(公告)日：2018-09-13

    申请号：US15979223

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： Kshitij A. DOSHI ,  Thomas WILLHALM

    IPC: G06F12/0804 ,  G06F12/0815 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084

    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.

    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS
    16.
    发明公开
    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS 审中-公开

    公开(公告)号：US20230222025A1

    公开(公告)日：2023-07-13

    申请号：US18124453

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM ,  Marcos E. CARRANZA

    IPC: G06F11/00 ,  G06F11/14

    CPC classification number: G06F11/008 ,  G06F11/142

    Abstract: Reliability, availability, and serviceability (RAS)-based memory domains can enable applications to store data in memory domains having different degrees of reliability to reduce downtime and data corruption due to memory errors. In one example, memory resources are classified into different RAS-based memory domains based on their expected likelihood of encountering errors. The mapping of memory resources into RAS-based memory domains can be dynamically managed and updated when information indicative of reliability (such as the occurrence of errors or other information) suggests that a memory resource is becoming less reliable. The RAS-based memory domains can be exposed to applications to enable applications to allocate memory in high reliability memory for critical data.

    SOFTWARE-ASSISTED SPARSE MEMORY
    17.
    发明申请
    SOFTWARE-ASSISTED SPARSE MEMORY 有权

    公开(公告)号：US20220318132A1

    公开(公告)日：2022-10-06

    申请号：US17847026

    申请日：2022-06-22

    Applicant: Intel Corporation

    Inventor： Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Karthik KUMAR

    IPC: G06F12/02

    Abstract: Methods and apparatus for software-assisted sparse memory. A processor including a memory controller is configured to implement one or more portions of the memory space for memory accessed via the memory controller as sparse memory regions. The amount of physical memory used for a sparse memory region is a fraction of the address range for the sparse memory region, where only non-zero data are written to the physical memory. Mechanisms are provided to detect memory access requests for memory in a sparse memory region and perform associated operations, while non-sparse memory access operations are performed when accessing memory that is not in a sparse memory region. Interfaces are provided to enable software to request allocation of a new sparse memory region or allocate sparse memory from an existing sparse memory region. Operations associated with access to sparse memory regions include detecting whether data for read and write request are all zeros.

    DYNAMIC LOAD BALANCING FOR POOLED MEMORY
    18.
    发明申请
    DYNAMIC LOAD BALANCING FOR POOLED MEMORY 有权

    公开(公告)号：US20220197819A1

    公开(公告)日：2022-06-23

    申请号：US17691743

    申请日：2022-03-10

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Thomas WILLHALM ,  Marcos E. CARRANZA ,  Cesar Ignacio MARTINEZ SPESSOT

    IPC: G06F12/109 ,  G06F12/14

    Abstract: Examples described herein relate to a memory controller to allocate an address range for a process among multiple memory pools based on a service level parameters associated with the address range and performance capabilities of the multiple memory pools. In some examples, the service level parameters include one or more of latency, network bandwidth, amount of memory allocation, memory bandwidth, data encryption use, type of encryption to apply to stored data, use of data encryption to transport data to a requester, memory technology, and/or durability of a memory device.

    REMOTE MEMORY OPERATIONS
    20.
    发明申请
    REMOTE MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20180004687A1

    公开(公告)日：2018-01-04

    申请号：US15201373

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Narayan RANGANATHAN ,  Pete D. VOGT

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  H04L29/08 ,  H04L12/803

    Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.

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