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    Concept for Group Memory Write Instructions
    2.
    发明申请
    Concept for Group Memory Write Instructions 审中-公开

    公开(公告)号：US20190227737A1

    公开(公告)日：2019-07-25

    申请号：US16221743

    申请日：2018-12-17

    Applicant: Intel Corporation

    Inventor： Ginger GILSDORF ,  Karthik KUMAR ,  Thomas WILLHALM ,  Mark SCHMISSEUR ,  Francesc GUIM BERNAT

    IPC: G06F3/06

    Abstract: Examples relate to a method for a memory module, a method for a memory controller, a method for a processor, to a memory module controller device or apparatus, to a memory controller device or apparatus, to a processor device or apparatus, a memory module, a memory controller, a processor, a computer system and a computer program. The method for the memory module comprises obtaining one or more memory write instructions of a group memory write instruction. The group memory write instruction comprises a plurality of memory write instructions to be executed atomically. The one or more memory write instructions relate to one or more memory addresses associated with memory of the memory module. The method comprises executing the one or more memory write instructions using previously unallocated memory of the memory module. The method comprises obtaining a commit instruction for the group memory write instruction. The method comprises updating the one or more memory addresses based on the previously unallocated memory used for executing the one or more memory write instructions after obtaining the commit instruction for the group memory write instruction.

    SYSTEMS, METHODS AND APPARATUS FOR MEMORY ACCESS AND SCHEDULING
    5.
    发明申请
    SYSTEMS, METHODS AND APPARATUS FOR MEMORY ACCESS AND SCHEDULING 审中-公开

    公开(公告)号：US20190102090A1

    公开(公告)日：2019-04-04

    申请号：US15719729

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Mark SCHMISSEUR

    IPC: G06F3/06 ,  G06F9/48

    Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.

    MEMORY ALLOCATION BASED ON TIME
    10.
    发明公开
    MEMORY ALLOCATION BASED ON TIME 审中-公开

    公开(公告)号：US20240028505A1

    公开(公告)日：2024-01-25

    申请号：US18375477

    申请日：2023-09-30

    Applicant: Intel Corporation

    Inventor： Sharanyan SRIKANTHAN ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos E. CARRANZA

    IPC: G06F12/02

    CPC classification number: G06F12/023

    Abstract: Examples described herein relate to allocation of an amount of memory for a time duration based on receipt of a request to allocate an amount of memory for a time duration. The request can include a configuration that requests an allocation of the amount of memory and the configuration specifies a time tier and/or the time duration. The request can specify one or more of: a request identifier, the amount of memory to allocate, or a requested time duration to reserve the amount of memory.

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