公开(公告)号：US09881659B2

公开(公告)日：2018-01-30

申请号：US14866579

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Tomishima Shigeki ,  Kuljit S. Bains ,  Tomer Levy

IPC: G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

公开(公告)号：US09722663B2

公开(公告)日：2017-08-01

申请号：US14229460

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenein ,  James M. Shehadi

IPC: H04B3/46 ,  H04B3/487 ,  G06F11/00 ,  G01R31/3185 ,  G01R31/28

CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.