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    Throttling support for row-hammer counters
    5.
    发明授权
    Throttling support for row-hammer counters 有权
    节流支持行锤计数器

    公开(公告)号：US09251885B2

    公开(公告)日：2016-02-02

    申请号：US13730181

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Zvika Greenfield ,  Tomer Levy

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40607 ,  G06F13/1605 ,  G11C11/40603 ,  G11C11/40611

    Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.

    Abstract translation: 调节内存访问命令。 在一段时间内监视访问存储设备的行。 时间框架被划分为至少两个子帧。 如果在第一子帧期间的任何行的访问次数超过第一阈值，则以第一速率限制对所访问的行的访问。 如果访问行的访问次数不超过第一个阈值，则不访问被访问的行。 第一个阈值与物理上与访问行相邻的行的数据损坏风险相关。 如果在第二子帧期间对所访问的行的访问次数超过第二阈值，则以第二速率限制对所访问的行的访问。 如果访问行的访问次数不超过第二个阈值，则不访问被访问的行。 第二阈值大于第一阈值。 第二节流率大于第一节流速率。

    PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE
    8.
    发明申请
    PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE 有权
    在银行集团架构的存储设备中预先存储和刷新银行

    公开(公告)号：US20160254044A1

    公开(公告)日：2016-09-01

    申请号：US14865754

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

    Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

    Abstract translation: 存储器子系统刷新管理使得命令能够使用单个命令访问跨不同银行组的一个或多个识别的银行。 每个银行组分别单独发送在单独的银行组中发送标识银行或银行的命令，该命令可以导致存储设备访问不同银行组中的银行。 该命令可以是刷新命令。 该命令可以是预充电命令。

    INTERFERENCE TESTING
    9.
    发明申请
    INTERFERENCE TESTING 有权
    干扰测试

    公开(公告)号：US20150280781A1

    公开(公告)日：2015-10-01

    申请号：US14229460

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenien ,  James M. Shehadi

    IPC: H04B3/46

    CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

    Abstract translation: 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。

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