公开(公告)号：US12063280B2

公开(公告)日：2024-08-13

申请号：US18456102

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L9/00 ,  H04L9/32 ,  H04L41/5009 ,  H04L67/562

CPC classification number: H04L67/51 ,  H04L9/3278 ,  H04L41/5009 ,  H04L67/562 ,  H04L9/50

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.

公开(公告)号：US11941409B2

公开(公告)日：2024-03-26

申请号：US16914331

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Asad Azam ,  Jenny M. Pelner ,  Vincent Zimmer ,  Rajaram Regupathy

IPC: G06F9/44 ,  G06F9/4401

CPC classification number: G06F9/4403 ,  G06F2212/60

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

公开(公告)号：US11875147B2

公开(公告)日：2024-01-16

申请号：US17412806

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Vincent Zimmer ,  Jiewen Yao

IPC: G06F8/71 ,  G06F8/65

CPC classification number: G06F8/71 ,  G06F8/65

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

公开(公告)号：US11870669B2

公开(公告)日：2024-01-09

申请号：US17556051

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L43/0817 ,  H04L43/0894 ,  G06N20/00 ,  H04L41/5009 ,  H04L43/0864

CPC classification number: H04L43/0817 ,  G06N20/00 ,  H04L41/5009 ,  H04L43/0864 ,  H04L43/0894

Abstract: An apparatus to facilitate at-scale telemetry using interactive matrix for deterministic microservices performance is disclosed. The apparatus includes one or more processors to: receive user input comprising an objective or task corresponding to scheduling a microservice for a service, wherein the objective or task may include QoS, SLO, ML feedback; identify interaction matrix components in an interaction matrix that match the objective or tasks for the microservice; identify knowledgebase components in knowledgebase that match the objective or tasks for the microservice; and determine a scheduling operation for the microservice, the scheduling operation to deploy the microservice in a configuration that is in accordance with the objective or task, wherein the configuration comprises a set of hardware devices and microservice interaction points determined based on the interaction matrix components and the knowledgebase components.

公开(公告)号：US11570264B1

公开(公告)日：2023-01-31

申请号：US17557604

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Subrata Banik ,  Marcos Carranza ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: H04L67/51 ,  H04L41/5009 ,  H04L9/32 ,  H04L67/562 ,  H04L9/00

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.

公开(公告)号：US20220197678A1

公开(公告)日：2022-06-23

申请号：US17131289

申请日：2020-12-22

Applicant: INTEL CORPORATION

Inventor： Rajesh Poornachandran ,  Vincent Zimmer ,  Prashant Dewan

IPC: G06F9/455 ,  G06F9/38 ,  G06F9/30

Abstract: Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention. A processor embodiment includes registers, evaluator, and execution unit. The registers are to store rules which specify actions to be taken with respect to one or more instructions. The evaluator is to detect a request to execute a first instruction and to evaluate the first instruction based on the rules stored in the one or more registers. The evaluator is further to block execution of the first instruction when a first rule corresponding to the first instruction specifies that execution of the first instruction is prohibited, and to allow execution of the first instruction when there is no rule in the one or more registers specifying that the execution of the first instruction is prohibited. The execution unit is to execute the first instruction when the evaluator allows execution of the first instruction.

公开(公告)号：US11249748B2

公开(公告)日：2022-02-15

申请号：US16649911

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Vincent Zimmer ,  Jiewen Yao

IPC: G06F8/71 ,  G06F8/65

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

公开(公告)号：US11074085B2

公开(公告)日：2021-07-27

申请号：US16642318

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Yah Wen Ho ,  Vincent Zimmer ,  Tung Lun Loo

IPC: G06F9/4401 ,  G06F13/42

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

公开(公告)号：US20210081538A1

公开(公告)日：2021-03-18

申请号：US17109081

申请日：2020-12-01

Applicant: Intel Corporation

Inventor： Vincent Zimmer ,  Subrata Banik ,  Rajaram Regupathy

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/79 ,  G06F9/4401 ,  G06F9/30 ,  G06F12/0811

Abstract: Systems, apparatuses and methods may provide for technology that initializes static random access memory (SRAM) of a processor in response to a reset of the processor, allocates the SRAM to one or more security enforcement operations, and triggers a multi-threaded execution of the one or more security enforcement operations before completion of a basic input output system (BIOS) phase. In one example, the multi-threaded execution is triggered independently of a dynamic RAM (DRAM) initialization.

公开(公告)号：US10761951B2

公开(公告)日：2020-09-01

申请号：US15856316

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Nagasubramanian Gurumoorthy ,  Vincent Zimmer

IPC: G06F11/00 ,  G06F11/20 ,  G05B19/042 ,  G06F21/57 ,  G06F30/15 ,  G06F30/34 ,  G06F30/392 ,  H04B1/40 ,  G06F117/08

Abstract: An apparatus to implement functional safety control logic (FSCL) in an autonomous driving system comprises a field-programmable gate array (FPGA) comprising logic elements to be partitioned into a first section to implement one or more safety cores and a second section to implement one or more non-safety cores, a memory to couple to the safety core or to the non-safety core, and a trusted execution environment (TEE) to couple to a remote administrator via a network and to apply a configuration received from the remote administrator to the FPGA. The safety core is to function as an active agent for FSCL during operation, and the non-safety core is to function as a failover agent during operation, and wherein the non-safety core is to perform a liveliness check on the safety core to monitor for a failover and to take over as the active agent in the event of a failover.