公开(公告)号：US20180069534A1

公开(公告)日：2018-03-08

申请号：US15558059

申请日：2016-03-24

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Shuichiro Yamamoto

IPC: H03K3/3565 ,  G11C11/413 ,  G11C11/412 ,  H02M7/42

CPC classification number: H03K3/3565 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C14/0054 ,  H02M7/42 ,  H03K3/02337 ,  H03K3/356

Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.

公开(公告)号：US20170005265A1

公开(公告)日：2017-01-05

申请号：US15125840

申请日：2015-03-06

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Minoru Kurosawa ,  Hiroshi Funakubo ,  Shuichiro Yamamoto

IPC: H01L49/00 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L49/00 ,  G11C11/16 ,  G11C14/0081 ,  G11C14/009 ,  H01L27/226 ,  H01L27/2436 ,  H03K3/356

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract translation: 晶体管包括：载流子通过其传导的压电电阻; 将载流子注入压电电阻器的源; 从压电电阻接收载流子的漏极; 定位成围绕压电电阻并向压敏电阻施加压力的压电材料; 以及向压电材料施加电压使得压电材料向压电电阻施加压力的栅极。

公开(公告)号：US20150070974A1

公开(公告)日：2015-03-12

申请号：US14543487

申请日：2014-11-17

Applicant: Japan Science and Technology Agency

Inventor： Yusuke Shuto ,  Shuichiro Yamamoto ,  Satoshi Sugahara

IPC: G11C14/00

CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1693

Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

Abstract translation: 存储电路包括：存储数据的双稳态电路（30）; 以非挥发性方式存储写在双稳态电路中的数据的非易失性元件（MTJ1，MTJ2），将以非易失性方式存储的数据恢复到双稳态电路中; 以及控制单元，其以非易失性方式存储写入双稳态电路中的数据，并且当不从双稳态电路读取数据或将数据写入双稳态电路的时间长于预定时间段时，切断对双稳态电路的电源，并且 不以非易失性方式存储写入双稳态电路中的数据，并且当不读或写数据的周期是双稳态电路的电源电压低于该周期期间的电压以从数据读取数据或将数据写入双稳态电路 比预定时间段短。