公开(公告)号：US20250113709A1

公开(公告)日：2025-04-03

申请号：US18895446

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Masahiro WATABE

IPC: H10K59/124 ,  H01L27/12 ,  H10K59/121 ,  H10K59/131

Abstract: A display device includes a light-emitting element, a first transistor, and a second transistor, the first transistor includes a first gate electrode, a first insulating film, a first oxide semiconductor layer, a second insulating film, and a first conductive layer provided on the second insulating film, and the second transistor includes the first insulating film, a second oxide semiconductor layer, a second insulating film, and a second gate electrode, wherein an etching rate of the first oxide semiconductor layer and the second semiconductor layer is less than 3 nm/min when the first oxide semiconductor layer and the second semiconductor layer are etched using an etching solution containing phosphoric acid as a main component at 40° C.

公开(公告)号：US20250113546A1

公开(公告)日：2025-04-03

申请号：US18897024

申请日：2024-09-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.

公开(公告)号：US20250113544A1

公开(公告)日：2025-04-03

申请号：US18895591

申请日：2024-09-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device according to an embodiment of the present invention includes: an oxide semiconductor layer; a first gate electrode facing the oxide semiconductor layer; a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; an electrode arranged in a region overlapping the oxide semiconductor layer in a plan view and electrically connected to the oxide semiconductor layer; and a metal nitride layer between the oxide semiconductor layer and the electrode, wherein the oxide semiconductor layer is polycrystalline, and an etching rate of the oxide semiconductor layer with respect to an etchant containing phosphoric acid as a main component is less than 3 nm/min at 40° C.

公开(公告)号：US20230169922A1

公开(公告)日：2023-06-01

申请号：US18104300

申请日：2023-02-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Masashi TSUBUKU

IPC: G09G3/3233

CPC classification number: G09G3/3233

Abstract: A display device including a substrate, a light-emitting element, a first transistor, and a second transistor, the first transistor including the first gate electrode on the substrate; a first insulating film on the first gate electrode, a first oxide semiconductor on the first insulating film, and having an area overlapping the first gate electrode, a second insulating film on the first oxide semiconductor, and a first conductive layer on the second insulating film, the second transistor including the first insulating film on the substrate, a second oxide semiconductor on the first insulating film, a second insulating film on the first oxide semiconductor and the second oxide semiconductor, and having a thickness smaller than a thickness of the first insulating film, a second gate electrode on the second insulating film, and having an area overlapping the second oxide semiconductor.