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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250113617A1

    公开(公告)日：2025-04-03

    申请号：US18887079

    申请日：2024-09-17

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Akihiro HANADA ,  Masahiro WATABE

    IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

    Abstract: A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. In a plan view, the second gate electrode is located with a space from each of the source electrode and the drain electrode. The second gate electrode is electrically connected to the first gate electrode.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240379865A1

    公开(公告)日：2024-11-14

    申请号：US18651909

    申请日：2024-05-01

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

    IPC: H01L29/786 ,  H01L29/417

    Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240312999A1

    公开(公告)日：2024-09-19

    申请号：US18588249

    申请日：2024-02-27

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

    IPC: H01L27/12

    CPC classification number: H01L27/1225 ,  H01L27/1251

    Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240178325A1

    公开(公告)日：2024-05-30

    申请号：US18519392

    申请日：2023-11-27

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

    IPC: H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/7869 ,  H01L29/0603 ,  H01L29/78696

    Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    9.
    发明公开
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240105819A1

    公开(公告)日：2024-03-28

    申请号：US18474389

    申请日：2023-09-26

    Applicant: Japan Display Inc.

    Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

    CPC classification number: H01L29/66969 ,  H01L21/02667 ,  H01L29/7869

    Abstract: A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.

    SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230387322A1

    公开(公告)日：2023-11-30

    申请号：US18449830

    申请日：2023-08-15

    Applicant: Japan Display Inc.

    Inventor： Takaya TAMARU ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Hajime WATAKABE

    IPC: H01L29/786 ,  H01L29/40 ,  H01L29/45

    CPC classification number: H01L29/7869 ,  H10K59/1213 ,  H01L29/45 ,  H01L29/401

    Abstract: A semiconductor device including: an oxide semiconductor layer including a first surface and a second surface opposite to the first surface; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; and a pair of first electrode being in contact with the first surface of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer including a region in which composition ratio of nitrogen is 2 percent or more within a depth range of 2 nanometers from the first surface in a region vicinity of an edge of at least one of the first electrode of the pair of first electrode.

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