公开(公告)号：US20150357562A1

公开(公告)日：2015-12-10

申请号：US14297689

申请日：2014-06-06

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/08 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633

Abstract: A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

Abstract translation: 提供半导体结构，电阻随机存取存储器单元结构以及半导体结构的制造方法。 半导体结构包括绝缘结构，停止层，金属氧化物层，电阻结构和电极材料层。 绝缘结构具有通孔，并且阻挡层形成在通路中。 在停止层上形成金属氧化物层。 电阻结构形成在金属氧化物层的外壁的底部。 在金属氧化物层上形成电极材料层。

公开(公告)号：US20150138871A1

公开(公告)日：2015-05-21

申请号：US14085839

申请日：2013-11-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu Lee ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79

Abstract: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.

Abstract translation: 提供了一种适用于包括晶体管和电阻性存储元件的电阻式存储单元的操作方法。 操作方法包括：在编程操作中，产生流过晶体管和电阻存储元件的编程电流，使得电阻性存储元件的电阻状态从第一电阻状态变为第二电阻状态; 并且在擦除操作中，产生从晶体管的阱区到电阻存储元件的擦除电流，但是保持擦除电流不流过晶体管，使得电阻性存储元件的电阻状态从第二电阻状态变为 第一个阻力状态。

公开(公告)号：US12198766B2

公开(公告)日：2025-01-14

申请号：US18172306

申请日：2023-02-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Hsiang-Lan Lung

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/24

Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

公开(公告)号：US12040015B2

公开(公告)日：2024-07-16

申请号：US17848521

申请日：2022-06-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C11/419 ,  G06F7/544 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F7/5443 ,  G11C13/0009 ,  G11C13/0069

Abstract: A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

公开(公告)号：US10957392B2

公开(公告)日：2021-03-23

申请号：US16233404

申请日：2018-12-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C16/04 ,  G11C16/08 ,  H01L29/792 ,  H01L29/788 ,  G11C16/26 ,  G06N3/063 ,  G06F7/544 ,  G11C16/10 ,  G11C11/54 ,  G06F7/38 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

公开(公告)号：US10476002B2

公开(公告)日：2019-11-12

申请号：US15690353

申请日：2017-08-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  G11C13/00 ,  H05K3/34

Abstract: A method for treating a semiconductor structure comprising memory devices is provided, wherein a forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

公开(公告)号：US20190138881A1

公开(公告)日：2019-05-09

申请号：US15803971

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G06N3/04

Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.

公开(公告)号：US09852791B1

公开(公告)日：2017-12-26

申请号：US15487458

申请日：2017-04-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Ming-Hsiu Lee ,  Kai-Chieh Hsu ,  Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C13/00 ,  H01L45/00 ,  H01L21/02 ,  H01L29/18

CPC classification number: G11C13/0059 ,  G06F21/70 ,  G06F21/73 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L21/02 ,  H01L29/18 ,  H01L45/00 ,  H01L45/06 ,  H04L9/0866 ,  H04L9/3278

Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.

公开(公告)号：US09515258B2

公开(公告)日：2016-12-06

申请号：US14729181

申请日：2015-06-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Chien-Hung Lu ,  Chin-Yi Tseng

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633 ,  H01L45/1683

Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

Abstract translation: 提供了包括绝缘层，第一电极层和第一屏障的存储结构。 绝缘层具有凹部。 第一电极层形成在凹部中并且具有第一顶表面。 第一阻挡层形成在绝缘层和第一电极层之间，并且具有比第一顶表面低的第二顶表面。 第一顶表面和第二顶表面比凹口的开口低。

公开(公告)号：US09514815B1

公开(公告)日：2016-12-06

申请号：US14877740

申请日：2015-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073

Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.

Abstract translation: 耦合到包括金属氧化物的可编程元件的电路被配置为执行程序验证操作，包括：程序操作和验证操作的初始循环以及随后的循环。 初始周期包括用于建立可编程元件的单元电阻的程序操作的初始实例，以及用于确定存储器单元的单元电阻是否在目标电阻范围内的验证操作的初始实例。 后续周期中的至少一个包括对可编程元件具有第二极性的附加脉冲以及验证操作的后续实例。 初始编程脉冲的第一极性和附加脉冲的第二极性具有相反的极性。 随后的程序操作实例包括将具有第一极性的后续编程脉冲施加到可编程元件。