公开(公告)号：US20240164224A1

公开(公告)日：2024-05-16

申请号：US18082609

申请日：2022-12-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun CHANG ,  Yu-Huan YEH ,  Chuan-Fu WANG

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.

公开(公告)号：US20190244895A1

公开(公告)日：2019-08-08

申请号：US16386891

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chi Tu ,  Chin-Chieh Yang ,  Wen-Ting Chu

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L27/08 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.

公开(公告)号：US20190221612A1

公开(公告)日：2019-07-18

申请号：US16178256

申请日：2018-11-01

Applicant: SK hynix Inc.

Inventor： Chi-Ho KIM ,  Eung-Rim HWANG ,  Sang-Hoon CHO

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/11507 ,  H01L27/22 ,  H01L27/11514 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/2481 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/02 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1286 ,  H01L45/1666

Abstract: An electronic device includes a semiconductor memory that includes: first and second lines spaced apart from each other and crossing each other; a third line spaced apart from the second line and crossing the second line; a first variable resistance element interposed between the first and second lines and overlapping an intersection of the first and second lines; a second variable resistance element interposed between the second and third lines and overlapping an intersection of the second and third lines, a part of the second variable resistance element generating a greater amount of heat than a part of the first variable resistance element when a current flows through the first variable resistance element in an opposite direction to a current flowing through the second variable resistance element; and a material layer serially connected with the second variable resistance element, disposed between the second and third lines, and exhibiting electrical resistance.

公开(公告)号：US20190198760A1

公开(公告)日：2019-06-27

申请号：US16287753

申请日：2019-02-27

Applicant: Toshiba Memory Corporation

Inventor： Takashi TACHIKAWA ,  Masumi SAITOH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/147 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a first metal oxide layer that is provided between the first conductive layer and the second conductive layer and includes at least one first metal element selected from the group consisting of aluminum (Al), gallium (Ga), zirconium (Zr), and hafnium (Hf); and a second metal oxide layer that is provided between the first metal oxide layer and the second conductive layer and includes at least one second metal element selected from the group consisting of zinc (Zn), titanium (Ti), tin (Sn), vanadium (V), niobium (Nb), tantalum (Ta), and tungsten (W). The first metal oxide layer includes a third metal element. The third metal element has a lower valence than a metal element having the highest atomic percent in the first metal oxide layer among the at least one first metal element.

公开(公告)号：US20190157346A1

公开(公告)日：2019-05-23

申请号：US16019346

申请日：2018-06-26

Applicant: SK hynix Inc.

Inventor： Jong Chul LEE

IPC: H01L27/24 ,  H01L45/00 ,  G06F3/06

CPC classification number: H01L27/2409 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16

Abstract: An electronic device having a semiconductor memory device is provided. The semiconductor memory device may include a lower interlayer insulating layer having a hole; an upper interlayer insulating layer disposed on the lower interlayer insulating layer; and a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer. The lower element may include a lower electrode and a selection element pattern disposed on the lower electrode. The upper element may include a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.

公开(公告)号：US20190067574A1

公开(公告)日：2019-02-28

申请号：US15690353

申请日：2017-08-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  H05K3/34

CPC classification number: H01L45/1641 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H05K3/3494

Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

公开(公告)号：US20180358556A1

公开(公告)日：2018-12-13

申请号：US15878257

申请日：2018-01-23

Applicant: SK hynix Inc.

Inventor： Dae-Gun KANG ,  Su-Jin CHAE ,  Sung-Kyu MIN ,  Myoung-Sub KIM ,  Chi-Ho KIM ,  Su-Yeon LEE

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/1675

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

公开(公告)号：US20180336947A1

公开(公告)日：2018-11-22

申请号：US16048502

申请日：2018-07-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gibson ,  R. Stanley Williams

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/008 ,  G11C2213/15 ,  G11C2213/52 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/146

Abstract: A memristor includes a bottom electrode, a top electrode, and an active region disposed therebetween. The active region has an electrically conducting filament in an electrically insulating medium, extending between the bottom electrode and the top electrode. The memristor further includes a temperature gradient element for controlling switching.

公开(公告)号：US20180309054A1

公开(公告)日：2018-10-25

申请号：US15755571

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty ,  Niloy Mukherjee

IPC: H01L45/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; a first oxide layer between the OEL and the bottom electrode; and a second oxide layer between the first oxide layer and the bottom electrode; wherein (a) a first plurality of oxygen vacancies are within the first oxide layer and are adjacent the OEL at a first concentration, (b) a second plurality of oxygen vacancies are within the first oxide layer and are adjacent the second oxide layer at a second concentration that is less than the first concentration, and (c) the first oxide layer includes a first oxide material different from a second oxide material included in the second oxide layer. Other embodiments are described herein.

公开(公告)号：US20180277753A1

公开(公告)日：2018-09-27

申请号：US15696119

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiko YAMAMOTO ,  Yosuke Murakami ,  Yusuke Arayashiki ,  Yusuke Kobayashi

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/55 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/148

Abstract: A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.