公开(公告)号：US20150102495A1

公开(公告)日：2015-04-16

申请号：US14051548

申请日：2013-10-11

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/482

CPC classification number: H01L24/30 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/64 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/181 ,  H05K3/222 ,  H05K3/284 ,  H05K2203/049 ,  H05K2203/173 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate, a first pad, a second, a first conductive element, a surface mount device, a first bonding wire and a molding compound layer. The first pad, the second pad, and the first conductive element are formed on the substrate. The surface mount device is mounted on the first pad and the second pad. The first bonding wire electrically connects the first conductive element and the first pad. The molding compound layer encapsulates the substrate, the first pad, the second pad, the first conductive element, the bonding wire and the surface mount device.

Abstract translation: 提供半导体封装。 半导体封装包括衬底，第一衬垫，第二衬底，第一导电元件，表面贴装器件，第一接合线和模塑复合层。 第一焊盘，第二焊盘和第一导电元件形成在基板上。 表面安装器件安装在第一焊盘和第二焊盘上。 第一接合线电连接第一导电元件和第一焊盘。 模塑复合层封装基板，第一焊盘，第二焊盘，第一导电元件，接合线和表面安装装置。

公开(公告)号：US20140002935A1

公开(公告)日：2014-01-02

申请号：US13892323

申请日：2013-05-13

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen ,  Yau-Wai Wong

IPC: H01L23/495 ,  H05K1/02

CPC classification number: H05K1/18 ,  H01L23/3185 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49558 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H02H9/046 ,  H05K1/0216 ,  H05K1/0245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Abstract translation: 印刷电路板（PCB）组件包括具有芯基板的PCB，PCB的第一表面上的多个导电迹线以及PCB的第二表面上的接地层。 导电迹线包括一对差分信号迹线。 在差分信号迹线之间设置介于其间的参考迹线。 连接器设置在多个导电迹线的一端。 半导体封装安装在多个导电迹线的另一端的第一表面上。

公开(公告)号：US20220353985A1

公开(公告)日：2022-11-03

申请号：US17858445

申请日：2022-07-06

Applicant: MediaTek Inc.

Inventor： Nan-Jang Chen

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/05

Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.

公开(公告)号：US20200022251A1

公开(公告)日：2020-01-16

申请号：US16581734

申请日：2019-09-24

Applicant: MediaTek Inc.

Inventor： Nan-Jang Chen

IPC: H05K1/02 ,  H05K1/05 ,  H01P3/08

Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. First non-ground nets and a ground net are disposed within a specific region on the top surface. A second non-ground net and a split ground net are disposed on the bottom surface. The second non-ground net is electrically connected to one of the first non-ground nets through a first via hole in the substrate. The second non-ground net is isolated from the split ground net by a gap. An outermost insulating layer on the bottom surface of the substrate covers the second non-ground net and the split ground net. A conductive layer is disposed on the outermost insulating layer corresponding to the specific region of the substrate in which the first non-ground nets and the ground net are arranged, such that the conductive layer overlaps with the first non-ground nets.

公开(公告)号：US10211134B2

公开(公告)日：2019-02-19

申请号：US15831408

申请日：2017-12-05

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.

公开(公告)号：US20180096922A1

公开(公告)日：2018-04-05

申请号：US15831408

申请日：2017-12-05

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H01L23/495

CPC classification number: H01L23/49589 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49544 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/14361 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/1904 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.

公开(公告)号：US20160293521A1

公开(公告)日：2016-10-06

申请号：US15185035

申请日：2016-06-17

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49544 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14361 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/1904 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2224/05599

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

Abstract translation: 半导体封装包括管芯焊盘，安装在管芯焊盘上的半导体管芯，多个引线，其包括沿管芯焊盘周边设置的电源引线，连接管芯焊盘的至少一个连接条， 连接杆的一侧和具有第一端子和第二端子的表面安装装置（SMD）。 第一端子通过第一接合线电连接到地平面。 第二端子通过第二接合线电连接功率电平。

公开(公告)号：US20160120034A1

公开(公告)日：2016-04-28

申请号：US14992011

申请日：2016-01-10

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen ,  Yau-Wai Wong

IPC: H05K1/18 ,  H01L23/495 ,  H01L23/31 ,  H02H9/04

CPC classification number: H05K1/18 ,  H01L23/3185 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49558 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H02H9/046 ,  H05K1/0216 ,  H05K1/0245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Abstract translation: 印刷电路板（PCB）组件包括具有芯基板的PCB，PCB的第一表面上的多个导电迹线以及PCB的第二表面上的接地层。 导电迹线包括一对差分信号迹线。 在差分信号迹线之间设置介于其间的参考迹线。 连接器设置在多个导电迹线的一端。 半导体封装安装在多个导电迹线的另一端的第一表面上。

公开(公告)号：US20150351245A1

公开(公告)日：2015-12-03

申请号：US14824210

申请日：2015-08-12

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H05K1/18 ,  H01L23/31 ,  H01L23/498 ,  H05K1/02 ,  H01L23/367 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/114 ,  H05K3/222 ,  H05K2201/066 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor package includes a substrate, a first conductive layer, a second conductive layer, a first surface mount device, a second surface mount device and a connection element. The first conductive layer is formed on the substrate and has a first pad and a second pad separated from the first pad. The second conductive layer is formed on the substrate and has a third pad and a fourth pad electrically connected with the third pad through the second conductive layer. The first surface mount device is mounted on the first pad and the third pad. The second surface mount device is mounted on the second pad and the fourth pad. The connection element electrically connects the first pad with the second pad.

Abstract translation: 半导体封装包括衬底，第一导电层，第二导电层，第一表面安装器件，第二表面安装器件和连接元件。 第一导电层形成在基板上，并具有与第一焊盘分离的第一焊盘和第二焊盘。 第二导电层形成在基板上，并具有通过第二导电层与第三焊盘电连接的第三焊盘和第四焊盘。 第一表面贴装装置安装在第一垫和第三垫上。 第二表面安装装置安装在第二垫和第四垫上。 连接元件将第一焊盘与第二焊盘电连接。

公开(公告)号：US20200352023A1

公开(公告)日：2020-11-05

申请号：US16929651

申请日：2020-07-15

Applicant: MediaTek Inc.

Inventor： Nan-Jang Chen

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/05

Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. A reference plane is embedded in the substrate and adjacent to the top surface. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate, the first signal net and the second signal net. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region in which the first signal net and the second signal net are arranged, such that the conductive layer overlaps with the first signal net.