公开(公告)号：US20180206339A1

公开(公告)日：2018-07-19

申请号：US15921676

申请日：2018-03-15

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen ,  Yau-Wai Wong

IPC: H05K1/18 ,  H01L23/495 ,  H05K1/02 ,  H01L23/31 ,  H02H9/04

Abstract: A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.

公开(公告)号：US08941221B2

公开(公告)日：2015-01-27

申请号：US13626899

申请日：2012-09-26

Applicant: Mediatek Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/495

CPC classification number: H01L23/49589 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a die pad, at least one semiconductor die mounted on the die pad, a plurality of leads disposed along peripheral edges of the die pad, at least one connecting bar for supporting the die pad, a first power bar disposed on one side of the connecting bar, a second power bar disposed on the other side of the connecting bar, and a connection member traversing the connecting bar and electrically connecting the first power bar with the second power bar.

Abstract translation: 半导体封装包括管芯焊盘，安装在管芯焊盘上的至少一个半导体管芯，沿着管芯焊盘的周边边缘设置的多个引线，至少一个用于支撑管芯焊盘的连接杆，设置在管芯焊盘上的第一电源棒 连接杆的一侧，设置在连接杆的另一侧的第二电源杆，以及横穿连接杆并将第一电源杆与第二电源条电连接的连接构件。

公开(公告)号：US20130082371A1

公开(公告)日：2013-04-04

申请号：US13626899

申请日：2012-09-26

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H01L23/495

CPC classification number: H01L23/49589 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a die pad, at least one semiconductor die mounted on the die pad, a plurality of leads disposed along peripheral edges of the die pad, at least one connecting bar for supporting the die pad, a first power bar disposed on one side of the connecting bar, a second power bar disposed on the other side of the connecting bar, and a connection member traversing the connecting bar and electrically connecting the first power bar with the second power bar.

Abstract translation: 半导体封装包括管芯焊盘，安装在管芯焊盘上的至少一个半导体管芯，沿着管芯焊盘的周边边缘设置的多个引线，至少一个用于支撑管芯焊盘的连接杆，设置在管芯焊盘上的第一电源棒 连接杆的一侧，设置在连接杆的另一侧的第二电源杆，以及横穿连接杆并将第一电源杆与第二电源条电连接的连接构件。

公开(公告)号：US20250105111A1

公开(公告)日：2025-03-27

申请号：US18892608

申请日：2024-09-23

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H01L23/498 ,  H01F17/00 ,  H02H9/04 ,  H05K1/02

Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive layer and second conductive layer. The second conductive layer is disposed opposite to the first conductive layer. One of the first conductive layer and the second conductive layer includes a first grounding net and a first signal ball-pad. The first grounding net has a first ground void, and the first signal ball-pad is disposed in the first ground void. The first signal ball-pad has a first ball-pad diameter, the first ground void has a first ground void diameter, and a ratio of the first ground void diameter to the first ball-pad diameter is equal to or greater than 1.2.

公开(公告)号：US20180019192A1

公开(公告)日：2018-01-18

申请号：US15718141

申请日：2017-09-28

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/48 ,  H01L21/4846 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K3/222 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.

公开(公告)号：US20160300812A1

公开(公告)日：2016-10-13

申请号：US15185063

申请日：2016-06-17

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L27/32 ,  H01L23/60 ,  H01L23/498 ,  H01L23/367

CPC classification number: H01L24/49 ,  H01L21/48 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L27/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K3/222 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate has a first top surface. The first conductive layer is formed on the first top surface and has a first conductive element and a second conductive element separated from each other. The first SMD is mounted on the first top surface, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.

Abstract translation: 半导体封装包括第一衬底，第一导电层，第一表面贴装器件（SMD）和第一接合线。 第一基板具有第一顶表面。 第一导电层形成在第一顶表面上，并且具有彼此分离的第一导电元件和第二导电元件。 第一SMD安装在第一顶表面上，与第一导电元件重叠但是电隔离。 第一接合线将第一SMD与第一导电层电连接。

公开(公告)号：US11903121B2

公开(公告)日：2024-02-13

申请号：US17858445

申请日：2022-07-06

Applicant: MediaTek Inc.

Inventor： Nan-Jang Chen

IPC: H05K1/02 ,  H05K1/11 ,  H01P3/08 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K1/0219 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0227 ,  H05K1/05 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/18

Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.

公开(公告)号：US10485095B2

公开(公告)日：2019-11-19

申请号：US15877396

申请日：2018-01-23

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen

IPC: H05K1/02 ,  H05K1/11 ,  H01P3/08 ,  H05K1/05 ,  H05K1/18

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.

公开(公告)号：US09392696B2

公开(公告)日：2016-07-12

申请号：US14824210

申请日：2015-08-12

Applicant: MEDIATEK Inc.

Inventor： Nan-Jang Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/18 ,  H01L23/367 ,  H05K1/11 ,  H01L23/498 ,  H05K1/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K1/181 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/114 ,  H05K3/222 ,  H05K2201/066 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor package includes a substrate, a first conductive layer, a second conductive layer, a first surface mount device, a second surface mount device and a connection element. The first conductive layer is formed on the substrate and has a first pad and a second pad separated from the first pad. The second conductive layer is formed on the substrate and has a third pad and a fourth pad electrically connected with the third pad through the second conductive layer. The first surface mount device is mounted on the first pad and the third pad. The second surface mount device is mounted on the second pad and the fourth pad. The connection element electrically connects the first pad with the second pad.

Abstract translation: 半导体封装包括衬底，第一导电层，第二导电层，第一表面安装器件，第二表面安装器件和连接元件。 第一导电层形成在基板上，并具有与第一焊盘分离的第一焊盘和第二焊盘。 第二导电层形成在基板上，并具有通过第二导电层与第三焊盘电连接的第三焊盘和第四焊盘。 第一表面贴装装置安装在第一垫和第三垫上。 第二表面安装装置安装在第二垫和第四垫上。 连接元件将第一焊盘与第二焊盘电连接。

公开(公告)号：US09269653B2

公开(公告)日：2016-02-23

申请号：US13892323

申请日：2013-05-13

Applicant: MEDIATEK INC.

Inventor： Nan-Jang Chen ,  Yau-Wai Wong

IPC: H05K7/10 ,  H01L23/495 ,  H05K1/02

CPC classification number: H05K1/18 ,  H01L23/3185 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49558 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H02H9/046 ,  H05K1/0216 ,  H05K1/0245 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Abstract translation: 印刷电路板（PCB）组件包括具有芯基板的PCB，PCB的第一表面上的多个导电迹线以及PCB的第二表面上的接地层。 导电迹线包括一对差分信号迹线。 在差分信号迹线之间设置介于其间的参考迹线。 连接器设置在多个导电迹线的一端。 半导体封装安装在多个导电迹线的另一端的第一表面上。