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11.发明公开公开(公告)号：US20240086075A1
公开(公告)日：2024-03-14
申请号：US17943082
申请日：2022-09-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aswin Thiruvengadam , Vamsi Pavan Rayaprolu
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
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公开(公告)号：US11783185B2
公开(公告)日：2023-10-10
申请号：US17706256
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Joshua Phelps , Peter B. Harrington
CPC classification number: G06N3/08 , G06F11/008 , G06F11/2257 , G06F11/2263 , G06N3/04 , G11C29/50 , G11C2029/5004
Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.
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公开(公告)号：US20210090674A1
公开(公告)日：2021-03-25
申请号：US17111755
申请日：2020-12-04
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
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公开(公告)号：USD893484S1
公开(公告)日：2020-08-18
申请号：US29673181
申请日：2018-12-12
Applicant: Micron Technology, Inc.
Designer： Daniel G. Scobee , Aleksandr Semenuk , Aswin Thiruvengadam
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公开(公告)号：US20200174064A1
公开(公告)日：2020-06-04
申请号：US16209393
申请日：2018-12-04
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Sivagnanam Parthasarathy , Frederick Jensen
Abstract: A request to perform a test with one or more memory components can be received. Available test resources of a test platform that is associated with memory components can be determined. The desired characteristics of the one or more memory components that are specified by the test can be determined. One or more of the available test resources of the test platform to the test can be assigned based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components of the test. Furthermore, the test can be performed with the assigned one or more of the available test resources of the test platform.
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Patent Agency Ranking
公开(公告)号：US10672470B1
公开(公告)日：2020-06-02
申请号：US16209352
申请日：2018-12-04
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Sivagnanam Parthasarathy , Daniel Scobee
Abstract: An indication that a test resource of a test platform has failed can be received. The test resource can be associated with performing a portion of a test of memory components. A characteristic of the test resource that failed can be determined. Another test resource of the test platform can be identified based on the characteristic of the test resource that failed. The portion of the test of memory components can be performed based on the another test resource of the test platform.
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公开(公告)号：US10431319B2
公开(公告)日：2019-10-01
申请号：US15802521
申请日：2017-11-03
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
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公开(公告)号：US20190138443A1
公开(公告)日：2019-05-09
申请号：US15802652
申请日：2017-11-03
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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公开(公告)号：US20190006000A1
公开(公告)日：2019-01-03
申请号：US16122523
申请日：2018-09-05
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Hernan A. Castro
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
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公开(公告)号：US20150149838A1
公开(公告)日：2015-05-28
申请号：US14612103
申请日：2015-02-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
IPC: G06F3/06
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
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