公开(公告)号：US11923030B2

公开(公告)日：2024-03-05

申请号：US17888641

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42 ,  G11C29/50

CPC classification number: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/50004 ,  G11C29/783

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

公开(公告)号：US20240070008A1

公开(公告)日：2024-02-29

申请号：US17897910

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Ipsita Ghosh ,  Vamsi Pavan Rayaprolu

IPC: G06F11/07

CPC classification number: G06F11/0784 ,  G06F11/0757 ,  G06F11/0787

Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.

公开(公告)号：US11914890B2

公开(公告)日：2024-02-27

申请号：US18168300

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0625 ,  G06F3/0679

Abstract: A memory sub-system to, in response to a power up, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system. In response to a request to execute a memory access operation, interrupting the first loading process. A second loading process including loading a portion of the set of trim values corresponding to the request is executed. The memory access operation is executed using the portion of the set of trim values loaded into the one or more registers during the second loading process. Following execution of the memory access operation, the first loading process is resumed to load one or more unloaded trim values of the sequence of trim values.

公开(公告)号：US20240055046A1

公开(公告)日：2024-02-15

申请号：US17819567

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Aswin Thiruvengadam

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C7/24

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C7/24

Abstract: Methods, systems, and devices for a model for predicting memory system performance are described. A memory system may generate a set of read commands and perform a first set of read operations at a memory device according to the generated read commands. The memory system may generate information indicating a performance of the memory device based on the first set of read operations and may update one or more coefficients of a model that correlates the information with a change in a read window. In some cases, the memory system may model the change in a read window based on the information and update one or more parameters associated with read operations based on the modelled change in the read window. The memory system may perform a second set of read operations at the memory device using the one or more updated parameters.

公开(公告)号：US20240054046A1

公开(公告)日：2024-02-15

申请号：US17884076

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Vamsi Pavan Rayaprolu

IPC: G06F11/10 ,  G11C29/08

CPC classification number: G06F11/1044 ,  G11C29/08

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.

公开(公告)号：US20240036973A1

公开(公告)日：2024-02-01

申请号：US17877637

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

公开(公告)号：US11854649B2

公开(公告)日：2023-12-26

申请号：US17675592

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C7/04 ,  G06F3/064 ,  G11C16/08 ,  G11C16/26

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

公开(公告)号：US11836392B2

公开(公告)日：2023-12-05

申请号：US17450653

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Harish R. Singidi ,  Peter Feeley

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0611 ,  G06F3/0647

Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.

公开(公告)号：US11756636B2

公开(公告)日：2023-09-12

申请号：US17939594

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Christopher M. Smitchger

IPC: G11C7/22 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/3431 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3459

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric associated with data stored in a part of a block of the memory device; responsive to determining that the value of the data state metric satisfies a first threshold criterion, determining a first value reflecting a voltage distribution metric associated with at least the part of the block; determining a second value reflecting at least one of a deterioration slope indicative of a data deterioration rate associated with a first portion of the memory device or an error rate associated with a second portion of the memory device; feeding the first value and the second value to a neural network; and receiving, from the neural network, an instruction to perform a media management operation.

公开(公告)号：US20230266901A1

公开(公告)日：2023-08-24

申请号：US17675624

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0679

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.