公开(公告)号：US20140127907A1

公开(公告)日：2014-05-08

申请号：US13672460

申请日：2012-11-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Guangjun Yang

IPC: H01L21/311 ,  C09K13/04 ,  C09K13/00

CPC classification number: C09K13/00 ,  C09K13/04 ,  C23F1/10 ,  C23F1/12 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138

Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.

Abstract translation: 形成半导体器件结构和二氧化硫蚀刻化学品的方法。 可以是等离子体化学的方法和化学物质包括使用二氧化硫和卤素类化合物在具有低特征宽度粗糙度的临界尺寸下形成诸如抗蚀剂材料的图案形成材料的修剪图案，具有低的 与使用常规化学和修整方法形成的修剪特征相比，空间宽度粗糙度没有过高的高度损失，并且没有显着的不规则性。

公开(公告)号：US11502085B2

公开(公告)日：2022-11-15

申请号：US16830662

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L27/108 ,  H01L49/02 ,  G11C5/02 ,  G11C5/10 ,  G11C11/402

Abstract: Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US11476255B2

公开(公告)日：2022-10-18

申请号：US17016609

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L27/108

Abstract: A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars. Metal material is formed in individual of the openings directly against the upper source/drain region of the individual pillars and atop the intervening material laterally outside of the openings. The metal material that is atop the intervening material interconnects the metal material that is in the individual openings. The metal material is removed back to have an uppermost surface that is no higher than an uppermost surface of the intervening material and to disconnect it from interconnecting the metal material that is in the individual openings and thereby form a laterally-isolated individual metal-material plug in the individual openings.

公开(公告)号：US20220285357A1

公开(公告)日：2022-09-08

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20210305254A1

公开(公告)日：2021-09-30

申请号：US16830662

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L27/108 ,  H01L49/02 ,  G11C11/402 ,  G11C5/10 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US10957549B2

公开(公告)日：2021-03-23

申请号：US16154088

申请日：2018-10-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L21/308 ,  H01L21/764 ,  H01L25/18 ,  H01L21/033 ,  H01L21/768

Abstract: A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.

公开(公告)号：US20200312857A1

公开(公告)日：2020-10-01

申请号：US16902783

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

IPC: H01L27/108 ,  H01L21/764 ,  G11C11/408

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

公开(公告)号：US20200006113A1

公开(公告)日：2020-01-02

申请号：US16536187

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L21/764 ,  H01L21/02 ,  H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

公开(公告)号：US09105587B2

公开(公告)日：2015-08-11

申请号：US13672460

申请日：2012-11-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311 ,  C09K13/00 ,  C09K13/04 ,  H01L21/027 ,  H01L21/033

CPC classification number: C09K13/00 ,  C09K13/04 ,  C23F1/10 ,  C23F1/12 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138

Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.

Abstract translation: 形成半导体器件结构和二氧化硫蚀刻化学品的方法。 可以是等离子体化学的方法和化学物质包括使用二氧化硫和卤素类化合物在具有低特征宽度粗糙度的临界尺寸下形成诸如抗蚀剂材料的图案形成材料的修剪图案，具有低的 与使用常规化学和修整方法形成的修剪特征相比，空间宽度粗糙度没有过高的高度损失，并且没有显着的不规则性。

公开(公告)号：US20150194321A1

公开(公告)日：2015-07-09

申请号：US14151499

申请日：2014-01-09

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mark Kiehlbauch

IPC: H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/32137

Abstract: A method of processing a polysilicon-comprising composition comprises forming a first wall comprising at least one recess in polysilicon. A second wall comprising polysilicon is formed. Material other than polysilicon is deposited within the at least one recess and over the polysilicon of the second wall. The material is etched selectively relative to polysilicon to expose polysilicon of the second wall and to leave the material within the at least one recess in the first wall. The exposed polysilicon of the second wall is etched selectively relative to the material within the at least one recess in the first wall. Other methods are disclosed.

Abstract translation: 一种处理含多晶硅的组合物的方法包括形成包含多晶硅中的至少一个凹部的第一壁。 形成包括多晶硅的第二壁。 除了多晶硅之外的材料沉积在第二壁的至少一个凹部内和多晶硅上。 相对于多晶硅选择性地蚀刻材料以暴露第二壁的多晶硅并且将材料留在第一壁中的至少一个凹部内。 相对于第一壁中的至少一个凹部内的材料选择性地蚀刻第二壁的暴露的多晶硅。 公开了其他方法。