公开(公告)号：US20190096994A1

公开(公告)日：2019-03-28

申请号：US16200593

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/105 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/115 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US20150206761A1

公开(公告)日：2015-07-23

申请号：US14676338

申请日：2015-04-01

Applicant: Micron Technology, Inc.

Inventor： Janos Fucsko ,  David H. Wells ,  Patrick M. Flynn ,  Whonchee Lee

IPC: H01L21/306 ,  H01L21/302 ,  H01L21/311

CPC classification number: H01L21/30608 ,  H01L21/302 ,  H01L21/31116 ,  H01L21/76232 ,  H01L29/66818

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract translation: 单晶硅蚀刻方法包括提供其中具有至少一个沟槽的单晶硅衬底。 将单晶硅衬底暴露于底切单晶硅的各向异性蚀刻剂。 通过控制蚀刻的长度，可以产生单晶硅中的单晶硅岛或平滑的垂直壁。

公开(公告)号：US20130295726A1

公开(公告)日：2013-11-07

申请号：US13939082

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Janos Fucsko

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/228 ,  H01L27/24

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 一叠半导体材料板可以被图案化以将该板细分成多个。 导电层可以沿着片的侧壁边缘形成。 然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。 单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。 栅极材料可以沿着中间区域形成。 存储单元结构可以形成在电线的第二端。 多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。 一些实施例包括并入到集成电路中的存储器阵列。

公开(公告)号：US20180175145A1

公开(公告)日：2018-06-21

申请号：US15895882

申请日：2018-02-13

Applicant: Micron Technology , Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/764 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US09929233B2

公开(公告)日：2018-03-27

申请号：US15385783

申请日：2016-12-20

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/76 ,  H01L29/06 ,  H01L27/115 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US20220028865A1

公开(公告)日：2022-01-27

申请号：US17498468

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L27/108 ,  H01L29/786

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

公开(公告)号：US08669144B2

公开(公告)日：2014-03-11

申请号：US13939082

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Janos Fucsko

IPC: H01L21/82

CPC classification number: H01L21/768 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/228 ,  H01L27/24

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 一叠半导体材料板可以被图案化以将该板细分成多个。 导电层可以沿着片的侧壁边缘形成。 然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。 单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。 栅极材料可以沿着中间区域形成。 存储单元结构可以形成在电线的第二端。 多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。 一些实施例包括并入到集成电路中的存储器阵列。