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    Memory arrays
    1.
    发明授权
    Memory arrays 有权
    内存阵列

    公开(公告)号：US09559163B2

    公开(公告)日：2017-01-31

    申请号：US14480454

    申请日：2014-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian ,  Janos Fucsko

    IPC: H01L31/113 ,  H01L29/06 ,  H01L21/764 ,  H01L27/115 ,  H01L27/105 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

    Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。

    Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates
    2.
    发明授权
    Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates 有权
    处理半导体衬底的方法，半导体制造期间形成开口的方法，以及从半导体衬底上去除颗粒的方法

    公开(公告)号：US08969217B2

    公开(公告)日：2015-03-03

    申请号：US13948043

    申请日：2013-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

    IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  B08B3/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

    CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

    Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

    Abstract translation: 一些实施方案包括处理半导体衬底的方法。 衬底可以暴露于连续变化的一个或多个条件。 条件可以包括温度梯度，一种或多种淬灭蚀刻剂的组合物的浓度梯度，有助于除去颗粒的pH梯度和/或一种或多种有助于除去颗粒的组合物的浓度梯度。 可以通过将半导体衬底放置在流动的漂洗溶液浴中来赋予连续变化的条件，浴中具有至少两条在其中提供漂洗溶液的进料管线。 供给管线中的一个可以处于第一状态，另一个可以处于与第一条件不同的第二条件。 可以改变通过每个进料管提供给浴的冲洗溶液的相对量，以连续地改变浴内的状态。

    Memory Arrays
    3.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20140374833A1

    公开(公告)日：2014-12-25

    申请号：US14480454

    申请日：2014-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian ,  Janos Fucsko

    IPC: H01L29/06 ,  H01L27/105

    CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

    Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。

    Memory arrays
    7.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10170545B2

    公开(公告)日：2019-01-01

    申请号：US15895882

    申请日：2018-02-13

    Applicant: Micron Technology, Inc.

    Inventor： Zailong Bian ,  Janos Fucsko

    IPC: H01L29/76 ,  H01L29/06 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/105 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

    Methods Of Treating Semiconductor Substrates, Methods Of Forming Openings During Semiconductor Fabrication, And Methods Of Removing Particles From Over Semiconductor Substrates
    9.
    发明申请
    Methods Of Treating Semiconductor Substrates, Methods Of Forming Openings During Semiconductor Fabrication, And Methods Of Removing Particles From Over Semiconductor Substrates 有权
    半导体衬底处理方法，半导体制造过程中形成开口的方法以及从半导体衬底去除微粒的方法

    公开(公告)号：US20130302995A1

    公开(公告)日：2013-11-14

    申请号：US13948043

    申请日：2013-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

    IPC: H01L21/306

    CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

    Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

    Abstract translation: 一些实施方案包括处理半导体衬底的方法。 衬底可以暴露于连续变化的一个或多个条件。 条件可以包括温度梯度，一种或多种淬灭蚀刻剂的组合物的浓度梯度，有助于除去颗粒的pH梯度和/或一种或多种有助于除去颗粒的组合物的浓度梯度。 可以通过将半导体衬底放置在流动的冲洗溶液浴中来赋予连续变化的条件，浴中具有至少两条在其中提供漂洗溶液的进料管线。 供给管线中的一个可以处于第一状态，另一个可以处于与第一条件不同的第二条件。 可以改变通过每个进料管提供给浴的冲洗溶液的相对量，以连续地改变浴内的状态。

    SEMICONDUCTOR STRUCTURE FORMATION
    10.
    发明申请
    SEMICONDUCTOR STRUCTURE FORMATION 有权

    公开(公告)号：US20210202246A1

    公开(公告)日：2021-07-01

    申请号：US16729903

    申请日：2019-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Santanu Sarkar ,  Jerome A. Imonigie ,  Kent H. Zhuang ,  Josiah Jebaraj Johnley Muthuraj ,  Janos Fucsko ,  Benjamin E. Greenwood ,  Farrell M. Good

    IPC: H01L21/02 ,  H01L21/762

    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.

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