公开(公告)号：US20210265371A1

公开(公告)日：2021-08-26

申请号：US16799543

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Lifang Xu

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US12178041B2

公开(公告)日：2024-12-24

申请号：US18152647

申请日：2023-01-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H01L23/528 ,  G11C5/02 ,  G11C5/06 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12040274B2

公开(公告)日：2024-07-16

申请号：US17314485

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H10B41/27 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/535 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240186239A1

公开(公告)日：2024-06-06

申请号：US18440581

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/522 ,  H01L21/768 ,  H10B69/00

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H10B69/00

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US11978705B2

公开(公告)日：2024-05-07

申请号：US17643061

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Xiao Li ,  Jivaan Kishore Jhothiraman ,  Mohadeseh Asadolahi Baboli

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions. Memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240071919A1

公开(公告)日：2024-02-29

申请号：US17823472

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Mohad Baboli ,  Yiping Wang ,  Xiao Li ,  Lifang Xu ,  John M. Meldrim ,  Jivaan Kishore Jhothiraman ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76822 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L23/535

Abstract: A microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.

公开(公告)号：US20240071495A1

公开(公告)日：2024-02-29

申请号：US17896775

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Shuangqiang Luo ,  Silvia Borsari

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including method, are disclosed.

公开(公告)号：US11915974B2

公开(公告)日：2024-02-27

申请号：US17227734

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shuangqiang Luo ,  Alyssa N. Scarbrough

IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.

公开(公告)号：US11903211B2

公开(公告)日：2024-02-13

申请号：US17647238

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/41

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20240047349A1

公开(公告)日：2024-02-08

申请号：US17818279

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11582

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/11582

Abstract: Methods, systems, and devices for support structures for three dimensional memory arrays are described. For example, a portion of a memory die may formed at least in part from a stack of material layers deposited over a substrate, and the memory die may include a set of access lines in a staircase arrangement over the stack. At least a portion of the stack of material layers between the staircase arrangement and the substrate may be configured to be continuous, or uninterrupted, which may result in fewer physical discontinuities in the stack of material layers below the staircase arrangement. In some examples, at least a portion of the stack of material layers (e.g., conductive portions) in such a region may be electrically isolated from other portions of the memory die, which may support aspects of structural support while limiting electrical interaction with the other portions of the memory die.