公开(公告)号：US20170069603A1

公开(公告)日：2017-03-09

申请号：US15354467

申请日：2016-11-17

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  William R. Stephenson ,  Walter L. Moden

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/0228 ,  H01L21/2007 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/488 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L27/1157 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0615 ,  H01L2224/06156 ,  H01L2224/09517 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/1415 ,  H01L2224/14156 ,  H01L2224/16148 ,  H01L2224/17177 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48477 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.

Abstract translation: 半导体器件封装包括面对关系的第一和第二半导体管芯。 至少一组焊料凸块基本上沿着半导体晶片之间的中心线并且与第一和第二半导体晶片的集成电路可操作地耦合。 另一组焊料凸起从中心线横向偏移并且仅与第一半导体管芯的集成电路可操作地耦合。 另一组焊料凸块从中心线横向偏移并且仅与第二半导体管芯的集成电路可操作地耦合。 形成半导体器件封装的方法包括将第一和第二半导体晶片与彼此面对的有源表面对准，第一和第二半导体晶片各自包括沿着其中心线的键合焊盘和从其中心线横向偏移的附加焊盘。

公开(公告)号：US11996359B2

公开(公告)日：2024-05-28

申请号：US18312801

申请日：2023-05-05

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US09502369B2

公开(公告)日：2016-11-22

申请号：US14613636

申请日：2015-02-04

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  William R. Stephenson ,  Walter L. Moden

IPC: H01L23/02 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/0228 ,  H01L21/2007 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/488 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L27/1157 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0615 ,  H01L2224/06156 ,  H01L2224/09517 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/1415 ,  H01L2224/14156 ,  H01L2224/16148 ,  H01L2224/17177 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48477 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.

Abstract translation: 半导体器件封装包括面对关系的第一和第二半导体管芯。 至少一组焊料凸块基本上沿着半导体晶片之间的中心线并且与第一和第二半导体晶片的集成电路可操作地耦合。 另一组焊料凸起从中心线横向偏移并且仅与第一半导体管芯的集成电路可操作地耦合。 另一组焊料凸块从中心线横向偏移并且仅与第二半导体管芯的集成电路可操作地耦合。 形成半导体器件封装的方法包括将第一和第二半导体晶片与彼此面对的有源表面对准，第一和第二半导体晶片各自包括沿着其中心线的键合焊盘和从其中心线横向偏移的附加焊盘。

公开(公告)号：US20160225734A1

公开(公告)日：2016-08-04

申请号：US14613636

申请日：2015-02-04

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  William R. Stephenson ,  Walter L. Moden

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/0228 ,  H01L21/2007 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/488 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L27/1157 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0615 ,  H01L2224/06156 ,  H01L2224/09517 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/1415 ,  H01L2224/14156 ,  H01L2224/16148 ,  H01L2224/17177 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48477 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/92127 ,  H01L2224/92163 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.

Abstract translation: 半导体器件封装包括面对关系的第一和第二半导体管芯。 至少一组焊料凸块基本上沿着半导体晶片之间的中心线并且与第一和第二半导体晶片的集成电路可操作地耦合。 另一组焊料凸起从中心线横向偏移并且仅与第一半导体管芯的集成电路可操作地耦合。 另一组焊料凸块从中心线横向偏移并且仅与第二半导体管芯的集成电路可操作地耦合。 形成半导体器件封装的方法包括将第一和第二半导体晶片与彼此面对的有源表面对准，第一和第二半导体晶片各自包括沿着其中心线的键合焊盘和从其中心线横向偏移的附加焊盘。