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公开(公告)号：US20250157909A1
公开(公告)日：2025-05-15
申请号：US19022030
申请日：2025-01-15
Applicant: Micron Technology, Inc.
Inventor： David K. Ovard , Thomas Hein , Timothy M. Hollis , Walter L. Moden
IPC: H01L23/498 , H01L23/00
Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.
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公开(公告)号：US20250069631A1
公开(公告)日：2025-02-27
申请号：US18771448
申请日：2024-07-12
Applicant: Micron Technology, Inc.
Inventor： Martin Bach , Miljana Nenadovic , Hemant Madhewar , Mani Balakrishnan , Thomas Hein , Martin Brox
Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.
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公开(公告)号：US20250021430A1
公开(公告)日：2025-01-16
申请号：US18764003
申请日：2024-07-03
Applicant: Micron Technology, Inc.
Inventor： Casto Salobrena Garcia , Thomas Hein , Michael Dieter Richter
IPC: G06F11/10
Abstract: Methods, systems, and devices for metadata transfer using unassigned codes of an encoder are described. The method may include inputting data and metadata associated with the data into an encoder. The data may include a first set of codewords modulated using a first modulation scheme including symbols that each represent one bit of digital information. Further, the method may include generating, using the encoder, a first subset of a second set of codewords representative of the data and a second subset of the second set of codewords representative of the metadata. The second set of codewords may be modulated using a second modulation scheme including symbols that each represent more than one bit of digital information. Further, the method may include transmitting the data and the metadata using the second set of codewords.
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公开(公告)号：US20240289220A1
公开(公告)日：2024-08-29
申请号：US18658754
申请日：2024-05-08
Applicant: Micron Technology, Inc.
Inventor： Steffen Buch , Thomas Hein
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0787
Abstract: Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.
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公开(公告)号：US20240095119A1
公开(公告)日：2024-03-21
申请号：US18211472
申请日：2023-06-19
Applicant: Micron Technology, Inc.
Inventor： Peter Mayer , Thomas Hein , Martin Brox , Wolfgang Anton Spirkl , Michael Dieter Richter
CPC classification number: G06F11/1044 , G06F11/1016 , G06F11/1028 , G11C29/42
Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
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Patent Agency Ranking
公开(公告)号：US11870616B2
公开(公告)日：2024-01-09
申请号：US17157815
申请日：2021-01-25
Applicant: Micron Technology, Inc.
Inventor： Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Martin Brox , Thomas Hein , Michael Dieter Richter
CPC classification number: H04L25/4917 , H04L1/0003
Abstract: Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.
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公开(公告)号：US20230386527A1
公开(公告)日：2023-11-30
申请号：US18202584
申请日：2023-05-26
Applicant: Micron Technology, Inc.
Inventor： Peter Mayer , Wolfgang Anton Spirkl , Michael Dieter Richter , Martin Brox , Thomas Hein
CPC classification number: G11C5/147 , G11C5/148 , G11C11/56 , G11C7/1096 , G11C7/1063 , G11C7/109 , G11C7/1069 , G11C11/221 , G11C11/2273 , G11C11/5657
Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.
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公开(公告)号：US11621033B2
公开(公告)日：2023-04-04
申请号：US17145066
申请日：2021-01-08
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , Thomas Hein , Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter
IPC: G11C11/4076 , H01L27/00 , H04L27/00 , G11C7/10 , G11C11/4093
Abstract: Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.
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公开(公告)号：US11620241B2
公开(公告)日：2023-04-04
申请号：US17393819
申请日：2021-08-04
Applicant: Micron Technology, Inc.
Inventor： Michael Dieter Richter , Thomas Hein , Martin Brox , Peter Mayer , Wolfgang Anton Spirkl
Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.
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公开(公告)号：US11579988B2
公开(公告)日：2023-02-14
申请号：US17376728
申请日：2021-07-15
Applicant: Micron Technology, Inc.
Inventor： Michael Dieter Richter , Thomas Hein , Wolfgang Anton Spirkl , Martin Brox , Peter Mayer
Abstract: Methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. After detecting an error (e.g., in received control information), the memory device may enter a first state (e.g., a locked state) and may indicate to a host device that an error was detected, the state of the memory array before the error was detected, and/or at least a portion of a control signal carrying the received control information. The host device may diagnose a cause of the error based on receiving the indication of the error and/or the copy of the control signal. After identifying and/or resolving the cause of the error, the host device may transmit one or more commands (e.g., unlocking the memory device and returning the memory array to the original state) based on receiving the original state from the memory device.
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