公开(公告)号：US11080210B2

公开(公告)日：2021-08-03

申请号：US16123907

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F11/00 ,  G06F13/16 ,  G06F13/42 ,  G06F11/07

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

公开(公告)号：US20210233601A1

公开(公告)日：2021-07-29

申请号：US17233336

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu ,  Jiangli Zhu

IPC: G11C29/48 ,  G11C29/56 ,  G06F11/10 ,  G11C29/14 ,  G11C29/44 ,  G11C29/52

Abstract: A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

公开(公告)号：US20210208820A1

公开(公告)日：2021-07-08

申请号：US17301044

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Cheng Yuan Wu ,  Ying Yu Tai

IPC: G06F3/06

Abstract: A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

公开(公告)号：US10991445B2

公开(公告)日：2021-04-27

申请号：US16123911

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu ,  Jiangli Zhu

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/56 ,  G06F11/10 ,  G11C29/14 ,  G11C29/52

Abstract: A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component.

公开(公告)号：US20210019182A1

公开(公告)日：2021-01-21

申请号：US16913751

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Jason Duong ,  Chih-Kuo Kao ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

IPC: G06F9/48 ,  G06F9/38 ,  G06F3/06

Abstract: Methods, systems, and devices for scheduling command execution are described. A memory sub-system can schedule command execution according to a type of command received. For a read operation, a memory sub-system can receive read commands for multiple memory dice. The memory sub-system can select a first memory die and execute a first set of read commands associated with the first memory die. The memory sub-system can then select a second memory die and execute a second set of read commands associated with the second memory die.

公开(公告)号：US20210019181A1

公开(公告)日：2021-01-21

申请号：US16855510

申请日：2020-04-22

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Wei Wang

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50 ,  G06F13/16 ,  G06F11/30

Abstract: Embodiments include methods, systems, devices, instructions, and media for internal management traffic regulation in memory devices. In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.

公开(公告)号：US20210019089A1

公开(公告)日：2021-01-21

申请号：US16916934

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20200026595A1

公开(公告)日：2020-01-23

申请号：US16039683

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Ning Chen ,  Zhengang Chen ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/52

Abstract: A read operation to retrieve data from memory component and that bypasses a prior search for the data at a buffer in a read data path associated with the read operation can be performed. Responsive to performing the read operation that bypasses the prior search for the data at the buffer, the data is returned to a host system.

公开(公告)号：US20190243787A1

公开(公告)日：2019-08-08

申请号：US16162905

申请日：2018-10-17

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Gurpreet Anand ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F13/16 ,  G06F13/42 ,  G11C16/20 ,  G06F9/445

CPC classification number: G06F13/1684 ,  G06F9/445 ,  G06F13/4234 ,  G06F13/4247 ,  G11C16/20

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

公开(公告)号：US20250156101A1

公开(公告)日：2025-05-15

申请号：US19023021

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu ,  Ning Chen

IPC: G06F3/06

Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.