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公开(公告)号:US20210391429A1
公开(公告)日:2021-12-16
申请号:US17348811
申请日:2021-06-16
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Atsushi KUROKAWA , Masahiro SHIBATA , Hiroaki TOKUYA , Mari SAJI
IPC: H01L29/417 , H01L29/73 , H01L29/08
Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
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公开(公告)号:US20210242842A1
公开(公告)日:2021-08-05
申请号:US17168618
申请日:2021-02-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Hiroaki TOKUYA , Hideyuki SATO , Fumio HARIMA , Kenichi SHIMAMOTO , Satoshi TANAKA , Takayuki KAWANO , Ryoki SHIKISHIMA , Atsushi KUROKAWA
Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.
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公开(公告)号:US20210184022A1
公开(公告)日:2021-06-17
申请号:US17189043
申请日:2021-03-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yasunari UMEMOTO , Daisuke TOKUDA , Tsunekazu SAIMEI , Hiroaki TOKUYA
IPC: H01L29/737 , H01L29/417 , H01L29/732 , H01L23/00 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/20 , H01L29/205
Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
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公开(公告)号:US20190333887A1
公开(公告)日:2019-10-31
申请号:US16505390
申请日:2019-07-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yasunari UMEMOTO , Daisuke TOKUDA , Tsunekazu SAIMEI , Hiroaki TOKUYA
IPC: H01L23/00 , H01L29/205 , H01L29/732 , H01L29/737 , H01L29/66 , H01L29/20 , H01L29/08 , H01L29/06 , H01L29/417
Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
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