公开(公告)号：US20200006265A1

公开(公告)日：2020-01-02

申请号：US16452637

申请日：2019-06-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

公开(公告)号：US20210035922A1

公开(公告)日：2021-02-04

申请号：US16943243

申请日：2020-07-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki TOKUYA ,  Masahiro SHIBATA ,  Akihiko OZAKI ,  Satoshi GOTO ,  Fumio HARIMA ,  Atsushi KUROKAWA

IPC: H01L23/00 ,  H01L29/737 ,  H01L27/082 ,  H01L23/498 ,  H01L23/66

Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

公开(公告)号：US20240153704A1

公开(公告)日：2024-05-09

申请号：US18503801

申请日：2023-11-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki TOKUYA ,  Masayuki AOIKE ,  Masahiro SHIBATA

IPC: H01G4/08 ,  H01G4/30 ,  H01G4/33

CPC classification number: H01G4/085 ,  H01G4/306 ,  H01G4/33

Abstract: A capacitor including a lower layer electrode, a dielectric film, and an upper layer electrode sequentially laminated on a partial area of an upper surface serving as one surface of a substrate formed from a compound semiconductor from a side closest to the substrate is disposed. A coating formed from an insulating metal oxide or a silicon oxide is disposed on or above the dielectric film. When the upper surface is viewed in a plan, the coating extends throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge.

公开(公告)号：US20190006306A1

公开(公告)日：2019-01-03

申请号：US16006623

申请日：2018-06-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro SHIBATA ,  Daisuke TOKUDA ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Yasunari UMEMOTO

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05086 ,  H01L2224/05547 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082

Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.

公开(公告)号：US20220157748A1

公开(公告)日：2022-05-19

申请号：US17649287

申请日：2022-01-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mayuka ONO ,  Motoji TSUDA ,  Fumio HARIMA ,  Koshi HIMEDA ,  Hiroaki TOKUYA

IPC: H01L23/66 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H05K1/18 ,  H01L23/498

Abstract: A mounting substrate has one main surface (a first main surface). An electronic component has a first face, a second face, and a side face, and is provided on the one main surface of the mounting substrate. A solder bump is disposed between the mounting substrate and the electronic component, and electrically connects the mounting substrate and the electronic component. A resin layer is provided on the one main surface of the mounting substrate to cover the electronic component. The first face is a face of the electronic component at a side opposite to the mounting substrate. The side face of the electronic component is in contact with the resin layer. A space is provided between at least a part of the first face and the resin layer in a thickness direction of the mounting substrate.

公开(公告)号：US20200161226A1

公开(公告)日：2020-05-21

申请号：US16749904

申请日：2020-01-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Kazuya KOBAYASHI ,  Yuichi SANO

IPC: H01L23/495 ,  H01L23/00

Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.

公开(公告)号：US20180233475A1

公开(公告)日：2018-08-16

申请号：US15954420

申请日：2018-04-16

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66 ,  H01L29/20 ,  H01L29/732 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20170077054A1

公开(公告)日：2017-03-16

申请号：US15361336

申请日：2016-11-25

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20160315060A1

公开(公告)日：2016-10-27

申请号：US15202749

申请日：2016-07-06

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20230395542A1

公开(公告)日：2023-12-07

申请号：US18452668

申请日：2023-08-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

IPC: H01L23/00 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L24/05 ,  H01L28/40 ,  H01L23/3171 ,  H01L27/0658 ,  H01L27/0676 ,  H01L2224/05558 ,  H01L28/20 ,  H01L23/3192 ,  H01L27/0664 ,  H01L2224/05573 ,  H01L2224/04105 ,  H01L23/528

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.