公开(公告)号：US20230352067A1

公开(公告)日：2023-11-02

申请号：US17730401

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Jaewon Lee

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1066 ,  G11C7/1093 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/14

Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.