公开(公告)号：US12009267B2

公开(公告)日：2024-06-11

申请号：US17203489

申请日：2021-03-16

Applicant: NXP B.V.

Inventor： Tushar Praful Merchant ,  Mark Douglas Hall ,  Anirban Roy

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/82385 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

公开(公告)号：US20220278226A1

公开(公告)日：2022-09-01

申请号：US17188868

申请日：2021-03-01

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/786 ,  H01L29/423 ,  H01L29/40

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.