公开(公告)号：US11605729B2

公开(公告)日：2023-03-14

申请号：US17188868

申请日：2021-03-01

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/786 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11521

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

公开(公告)号：US20220310786A1

公开(公告)日：2022-09-29

申请号：US17212159

申请日：2021-03-25

Applicant: NXP B.V.

Inventor： Tushar Praful Merchant ,  Mark Douglas Hall ,  Anirban Roy

IPC: H01L29/06 ,  H01L29/41 ,  H01L49/02 ,  H01L29/78 ,  H01L21/02

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

公开(公告)号：US20220274828A1

公开(公告)日：2022-09-01

申请号：US17188849

申请日：2021-03-01

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: B81C1/00

Abstract: A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors (61) and MEMS sensors (62) in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (12A-16A, 12B-16B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (49A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (13B-2, 15B-2) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (13B-1, 15B-1) on a second side of the MEMS sensor stack by forming a narrow trench opening (54) in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

公开(公告)号：US20220310456A1

公开(公告)日：2022-09-29

申请号：US17212311

申请日：2021-03-25

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

公开(公告)号：US20220301936A1

公开(公告)日：2022-09-22

申请号：US17203489

申请日：2021-03-16

Applicant: NXP B.V.

Inventor： Tushar Praful Merchant ,  Mark Douglas Hall ,  Anirban Roy

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

公开(公告)号：US11776856B2

公开(公告)日：2023-10-03

申请号：US17212311

申请日：2021-03-25

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

公开(公告)号：US11769797B2

公开(公告)日：2023-09-26

申请号：US17212159

申请日：2021-03-25

Applicant: NXP B.V.

Inventor： Tushar Praful Merchant ,  Mark Douglas Hall ,  Anirban Roy

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/41 ,  H01L49/02 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0669 ,  H01L21/0228 ,  H01L21/0245 ,  H01L21/02532 ,  H01L28/60 ,  H01L29/413 ,  H01L29/7848

Abstract: A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

公开(公告)号：US11685647B2

公开(公告)日：2023-06-27

申请号：US17188849

申请日：2021-03-01

Applicant: NXP B.V.

Inventor： Mark Douglas Hall ,  Tushar Praful Merchant ,  Anirban Roy

IPC: B81C1/00

CPC classification number: B81C1/00031 ,  B81C1/00166 ,  B81C1/00349 ,  B81C2201/013

Abstract: A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors (61) and MEMS sensors (62) in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (12A-16A, 12B-16B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (49A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (13B-2, 15B-2) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (13B-1, 15B-1) on a second side of the MEMS sensor stack by forming a narrow trench opening (54) in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

公开(公告)号：US11670394B2

公开(公告)日：2023-06-06

申请号：US17405633

申请日：2021-08-18

Applicant: NXP B.V.

Inventor： Michiel Jos van Duuren ,  Guido Jozef Maria Dormans ,  Anirban Roy

IPC: G11C7/04 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/04 ,  G11C29/4401 ,  G11C2207/2254

Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.

公开(公告)号：US20230056133A1

公开(公告)日：2023-02-23

申请号：US17405633

申请日：2021-08-18

Applicant: NXP B.V.

Inventor： Michiel Jos van Duuren ,  Guido Jozef Maria Dormans ,  Anirban Roy

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/04

Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.