公开(公告)号：US20190341369A1

公开(公告)日：2019-11-07

申请号：US15968769

申请日：2018-05-02

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/538 ,  G01R31/28

Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20190164909A1

公开(公告)日：2019-05-30

申请号：US16114251

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US20180301418A1

公开(公告)日：2018-10-18

申请号：US15717923

申请日：2017-09-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

Abstract: A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.

公开(公告)号：US10079218B1

公开(公告)日：2018-09-18

申请号：US15619969

申请日：2017-06-12

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang-Chien ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/19 ,  H01L21/6835 ,  H01L22/14 ,  H01L22/20 ,  H01L2221/68359 ,  H01L2224/82105

Abstract: A conductive layer is formed on a first surface of a first carrier. The redistribution layer is formed on the conductive layer. Then an open-test is performed to the redistribution layer. Since the conductive layer and the redistribution layer constitute a closed loop, a load should be presented during the open-test if the redistribution layer is formed correctly. After the open-test is performed, the first carrier and the conductive layer are removed. Then a short-test is performed to the redistribution layer. No load is presented during the short-test if the redistribution layer is formed correctly since the redistribution layer constitutes an open loop. Therefore, whether the redistribution layer has flaws can be determined before the dies are boned on the redistribution layer. Thus, no waste of the good die occurs because of the flawed redistribution layer.

公开(公告)号：US20180190594A1

公开(公告)日：2018-07-05

申请号：US15717956

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/81

Abstract: A manufacturing method of a packaging structure is provided. First, a carrier is provided. A conductive layer is formed on the carrier. A conductive frame is formed on the conductive layer. The conductive frame is in contact with and electrically connected to the conductive layer. A chip is placed on the conductive layer. The conductive frame surrounds the chip. An insulation encapsulation is formed to encapsulate the chip, and the insulation encapsulation exposes an active surface of the chip. A redistribution layer is formed on the active surface of the chip. The redistribution layer extends from the active surface to the insulation encapsulation.

公开(公告)号：US12154863B2

公开(公告)日：2024-11-26

申请号：US17454742

申请日：2021-11-12

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/762 ,  H01L23/66 ,  H01Q1/22

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

公开(公告)号：US20240339443A1

公开(公告)日：2024-10-10

申请号：US18401694

申请日：2024-01-01

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/167 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/83

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.

公开(公告)号：US11532575B2

公开(公告)日：2022-12-20

申请号：US16562442

申请日：2019-09-06

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/78 ,  H01L23/552

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US11309296B2

公开(公告)日：2022-04-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US20210202440A1

公开(公告)日：2021-07-01

申请号：US17099801

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L23/36 ,  H01L25/00

Abstract: A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.