公开(公告)号：US20190252325A1

公开(公告)日：2019-08-15

申请号：US16035709

申请日：2018-07-16

Applicant: Powertech Technology Inc.

Inventor： Yu-Wei Chen ,  Hsuan-Chih Chang ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/3025

Abstract: A chip package structure including a first circuit structure, a chip, an electronic device, a first encapsulant, a second encapsulant, a plurality of through pillars, and an electromagnetic interference (EMI) shielding layer is provided. The chip has an active surface facing the first circuit structure. The electronic device has a connection surface facing the first circuit structure. The chip and the electronic device are disposed on opposite sides of the first circuit structure respectively. The first encapsulant encapsulates the chip. The second encapsulant encapsulates the electronic device. The through pillars penetrate the first encapsulant and are electrically connected to the first circuit structure. The EMI shielding layer covers the first encapsulant and the second encapsulant. The chip or the electronic device is grounded by the EMI shielding layer.

公开(公告)号：US20180315674A1

公开(公告)日：2018-11-01

申请号：US15497219

申请日：2017-04-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hsien-Wen Hsu ,  Yuan-Fu Lan ,  Hung-Hsin Hsu

IPC: H01L23/043 ,  H01L23/06 ,  H01L23/31 ,  H01L21/82 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/043 ,  H01L21/82 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L2221/1068 ,  H01L2224/10 ,  H01L2224/11

Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.

公开(公告)号：US09659884B2

公开(公告)日：2017-05-23

申请号：US15298234

申请日：2016-10-20

Applicant: Powertech Technology Inc.

Inventor： Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H05K1/09 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H05K1/18 ,  H05K2201/10204

Abstract: A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.