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公开(公告)号:US20150041978A1
公开(公告)日:2015-02-12
申请号:US14524718
申请日:2014-10-27
Applicant: Renesas Electronics Corporation
Inventor: Yoichiro KURITA
CPC classification number: H01L25/18 , H01L21/563 , H01L23/3128 , H01L23/3135 , H01L23/3157 , H01L23/481 , H01L23/49816 , H01L23/5226 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/17 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06593 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/19107 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
Abstract translation: 半导体器件100包括设置在平板状互连部件101的一侧的面上的第一半导体元件113,覆盖配线部件101的第一半导体元件113的一侧的面的绝缘树脂119和 第一半导体元件113的侧面和设置在布线部件101的另一侧的面上的第二半导体元件111.布线部件101具有这样的结构,其中布线层103,硅层105和绝缘层 依次形成膜107。 互连层103具有其中互连层103具有平板状绝缘部件和延伸穿过绝缘部件的导电部件的结构。 第一半导体元件113通过导电部件与第二半导体元件111电连接。
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公开(公告)号:US20130099390A1
公开(公告)日:2013-04-25
申请号:US13712224
申请日:2012-12-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yoichiro KURITA , Masaya KAWANO , Koji SOEJIMA
IPC: H01L23/538
CPC classification number: H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L23/522 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/02 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2221/68345 , H01L2221/68372 , H01L2224/02319 , H01L2224/02331 , H01L2224/02333 , H01L2224/02372 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/16137 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/19105 , H05K3/0058 , H05K3/284 , H05K3/4682 , H05K2201/0195 , H05K2201/09527 , H05K2201/096 , H05K2201/09972 , H05K2203/016 , H05K2203/0733 , H05K2203/1469 , H01L2924/00 , H01L2224/0401
Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
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