公开(公告)号：US09405678B2

公开(公告)日：2016-08-02

申请号：US14859991

申请日：2015-09-21

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G06F12/02 ,  G06F13/364 ,  G11C7/10 ,  G06F1/10 ,  G06F13/16 ,  G06F13/42 ,  H04L7/00 ,  H04L7/033

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

公开(公告)号：US20150341128A1

公开(公告)日：2015-11-26

申请号：US14817607

申请日：2015-08-04

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04B17/29 ,  H04L27/01 ,  H04L25/03

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。

公开(公告)号：US08948212B2

公开(公告)日：2015-02-03

申请号：US14154068

申请日：2014-01-13

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G11C7/10 ,  G06F1/10 ,  G06F13/16 ,  G06F13/42 ,  H04L7/00 ,  H04L7/033

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

公开(公告)号：US08817932B2

公开(公告)日：2014-08-26

申请号：US13967530

申请日：2013-08-15

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04L7/00 ,  H04L27/06

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。

公开(公告)号：US20230140420A1

公开(公告)日：2023-05-04

申请号：US17978468

申请日：2022-11-01

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC: H04L25/03 ,  H04L25/497 ,  H04L7/027 ,  H04L25/06

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

公开(公告)号：US20220182158A1

公开(公告)日：2022-06-09

申请号：US17557518

申请日：2021-12-21

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04B17/29 ,  H04L25/03 ,  H04L27/01 ,  H04B17/21 ,  G01R31/317 ,  H04L1/20 ,  H04L1/24 ,  H04L7/033 ,  G06F11/08

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

公开(公告)号：US20210075651A1

公开(公告)日：2021-03-11

申请号：US16999853

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Bruno W. Garlepp ,  Grace Tsang ,  Mark A. Horowitz ,  Jared L. Zerbe ,  Jason C. Wei

IPC: H04L25/03 ,  H04L25/497 ,  H04L7/027 ,  H04L25/06

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

公开(公告)号：US10735116B2

公开(公告)日：2020-08-04

申请号：US16228470

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04B17/29 ,  H04L1/20 ,  H04L1/24 ,  H04L25/03 ,  H04B17/21 ,  G01R31/317 ,  H04L27/01 ,  H04L7/033 ,  G06F11/08 ,  H04L7/04 ,  H04L7/10

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

公开(公告)号：US20170031854A1

公开(公告)日：2017-02-02

申请号：US15222987

申请日：2016-07-29

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Abstract translation: 集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。 该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。 在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

公开(公告)号：US09544071B2

公开(公告)日：2017-01-10

申请号：US14817607

申请日：2015-08-04

Applicant: Rambus Inc.

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04B17/29 ,  H04L27/01 ,  H04L25/03 ,  G01R31/317 ,  H04L1/20 ,  H04L1/24 ,  H04L7/033 ,  G06F11/08 ,  H04B17/21 ,  H04L7/04 ,  H04L7/10

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。