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    Strobe acquisition and tracking
    11.
    发明授权
    Strobe acquisition and tracking 有权

    公开(公告)号：US10339990B2

    公开(公告)日：2019-07-02

    申请号：US15665312

    申请日：2017-07-31

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G01C7/02 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    INTERFACE CLOCK MANAGEMENT
    12.
    发明申请
    INTERFACE CLOCK MANAGEMENT 审中-公开

    公开(公告)号：US20180107623A1

    公开(公告)日：2018-04-19

    申请号：US15794148

    申请日：2017-10-26

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang

    IPC: G06F13/42 ,  G06F1/32

    CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D50/20

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE
    13.
    发明申请
    CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE 审中-公开
    从电可擦除可编程存储器件接收循环冗余校验（CRC）代码的控制器

    公开(公告)号：US20150349798A1

    公开(公告)日：2015-12-03

    申请号：US14823826

    申请日：2015-08-11

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: H03M13/09 ,  H03M13/00 ,  G06F11/10

    CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

    Remedial action indication
    14.
    发明授权
    Remedial action indication 有权

    公开(公告)号：US12253903B2

    公开(公告)日：2025-03-18

    申请号：US18140133

    申请日：2023-04-27

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F13/42 ,  H03M13/00 ,  H03M13/09 ,  H03M13/29 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1867

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Interface clock management
    15.
    发明授权
    Interface clock management 有权

    公开(公告)号：US12032508B2

    公开(公告)日：2024-07-09

    申请号：US18144349

    申请日：2023-05-08

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang

    IPC: G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

    CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/10 ,  Y02D10/00 ,  Y02D30/50

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    Strobe Acquisition and Tracking
    16.
    发明申请
    Strobe Acquisition and Tracking 审中-公开

    公开(公告)号：US20190392875A1

    公开(公告)日：2019-12-26

    申请号：US16459330

    申请日：2019-07-01

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G11C7/02 ,  G06F13/16

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Strobe Acquisition and Tracking
    18.
    发明申请
    Strobe Acquisition and Tracking 有权
    频闪采集跟踪

    公开(公告)号：US20140140149A1

    公开(公告)日：2014-05-22

    申请号：US13959633

    申请日：2013-08-05

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G11C7/02

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

    Interface clock management
    19.
    发明授权
    Interface clock management 有权

    公开(公告)号：US11681648B2

    公开(公告)日：2023-06-20

    申请号：US17559975

    申请日：2021-12-22

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang

    IPC: G06F1/00 ,  G06F13/42 ,  G06F1/3237 ,  G06F1/3206 ,  G06F1/3234

    CPC classification number: G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/10 ,  Y02D10/00 ,  Y02D30/50

    Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

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