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    Method for forming hole plug
    11.
    发明授权
    Method for forming hole plug 有权

    公开(公告)号：US10237983B2

    公开(公告)日：2019-03-19

    申请号：US14998135

    申请日：2015-12-23

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten

    IPC: H01K3/10 ,  H05K3/42 ,  H05K1/11 ,  H05K3/00

    Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AND METHOD OF MANUFACTURING THEREOF
    12.
    发明申请
    ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AND METHOD OF MANUFACTURING THEREOF 审中-公开

    公开(公告)号：US20190021177A1

    公开(公告)日：2019-01-17

    申请号：US16036913

    申请日：2018-07-16

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Toshiya Suzuki

    IPC: H05K3/46 ,  H05K3/00 ,  H05K1/11

    Abstract: A method for making an ultra-thin dielectric printed circuit board (PCB) is provided. A first side of a first conductive layer is removably coupled to a disposable base. A first ultra-thin dielectric layer and a second conductive layer are laminated to a second side of the first conductive layer, where the first ultra-thin dielectric layer is positioned between the first and second conductive layers, and the first ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may then be patterned to form electrical paths. The patterned second conductive layer is then filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may then be coupled to the second conductive layer. The disposable base may then be detached from the first conductive layer.

    Hole plug for thin laminate
    14.
    发明申请
    Hole plug for thin laminate 有权
    用于薄层压板的孔塞

    公开(公告)号：US20160219703A1

    公开(公告)日：2016-07-28

    申请号：US14998135

    申请日：2015-12-24

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten

    IPC: H05K1/11 ,  H05K3/00

    CPC classification number: H05K3/429 ,  H05K1/116 ,  H05K3/0094 ,  Y10T29/49165

    Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    Abstract translation: 提供了一种形成层压结构中的孔塞的方法。 形成层压体结构，在电介质层的第一侧上至少包括介电层和第一导电箔。 在层叠结构中形成未密封或盲孔，从电介质层的第二侧向第一导电箔延伸，并且至少部分地穿过电介质层，孔的孔深孔直径纵横比小于二十（ 20）到一（1）。 在另一个例子中，孔长宽比可以小于一（1）至1（1）。 然后，通过填充油墨可以沉积在孔中。 然后将通孔填充油墨干燥和/或固化以形成孔塞。

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    15.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 有权
    通过使用耐蚀材料的结构同时选择性的宽带划分

    公开(公告)号：US20140251663A1

    公开(公告)日：2014-09-11

    申请号：US14205337

    申请日：2014-03-11

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K1/036 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/0713 ,  H05K2203/0723

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Abstract translation: 提供了具有选择性地定位在第一介电层中的第一电介质层和第一电镀抗蚀剂的多层印刷电路板。 可以将第二电镀抗蚀剂选择性地定位在第一电介质层或第二电介质层中，第二电镀抗蚀剂与第一电镀抗蚀剂分离。 通孔延伸穿过第一电介质层，第一电镀抗蚀剂和第二电镀抗蚀剂。 除了沿第一电镀抗蚀剂和第二电镀抗蚀剂之间的长度之外，通孔的内表面镀有导电材料。 这形成了具有与第二通孔段电隔离的第一通路段的分隔电镀通孔。

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    17.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开

    公开(公告)号：US20200383204A1

    公开(公告)日：2020-12-03

    申请号：US16883671

    申请日：2020-05-26

    Applicant: Sanmina Corporation

    Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, JR.

    IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Simultaneous and selective wide gap partitioning of via structures using plating resist
    20.
    发明授权
    Simultaneous and selective wide gap partitioning of via structures using plating resist 有权

    公开(公告)号：US10667390B2

    公开(公告)日：2020-05-26

    申请号：US15723086

    申请日：2017-10-02

    Applicant: SANMINA CORPORATION

    Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

    IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

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