公开(公告)号：US09331002B2

公开(公告)日：2016-05-03

申请号：US13944783

申请日：2013-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/30 ,  H01L23/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

公开(公告)号：US20130299975A1

公开(公告)日：2013-11-14

申请号：US13944783

申请日：2013-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

公开(公告)号：US20130292850A1

公开(公告)日：2013-11-07

申请号：US13935963

申请日：2013-07-05

Applicant: STATS CHIPPAC, LTD.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Abstract translation: 半导体器件具有在载体上形成的导电柱。 第一半导体管芯安装在载体之间的导电柱之间。 密封剂沉积在第一半导体管芯和载体上并且围绕导电柱。 在第一半导体管芯上的密封剂的第一表面中形成凹部。 凹槽有倾斜或阶梯。 在密封剂的第一表面上形成第一互连结构。 第一互连结构遵循密封剂中的凹部的轮廓。 载体被移除。 在密封剂和第一半导体管芯的第二表面上形成第二互连结构。 第一和第二互连结构电连接到导电柱。 第二半导体管芯安装在凹槽中。 第三半导体管芯安装在凹槽和第二半导体管芯上。

公开(公告)号：US20130256861A1

公开(公告)日：2013-10-03

申请号：US13791375

申请日：2013-03-08

Applicant: STATS CHIPPAC LTD.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：电端子; 在电气端子周围的电路保护材料，并形成为具有凹陷垫体积; 电路保护材料顶表面上的可路由电路; 以及与电端子电连接的集成电路管芯。

公开(公告)号：US20130087928A1

公开(公告)日：2013-04-11

申请号：US13691578

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Nathapong Suthiwongsunthorn

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die.

Abstract translation: 半导体晶片具有在晶片的有效表面上形成的绝缘层。 在绝缘层上形成导电层。 第一通孔从半导体晶片的背面通过半导体晶片和绝缘层形成到导电层。 导电材料沉积在第一通孔中以形成导电TSV。 可以在第一通孔中沉积绝缘材料，以在导电通孔内形成绝缘芯。 在形成导电TSV之后，通过半导体晶片和绝缘层从导电TSV周围形成第二通孔，从半导体晶片的背表面到导电层。 绝缘材料沉积在第二通孔中以形成绝缘环形环。 导电通孔可以凹入半导体管芯的表面内或延伸到半导体管芯的表面之上。

公开(公告)号：US09893045B2

公开(公告)日：2018-02-13

申请号：US14971291

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H05K3/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/16 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US09048211B2

公开(公告)日：2015-06-02

申请号：US14017963

申请日：2013-09-04

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/36 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Abstract translation: 半导体器件具有形成在半导体管芯的第一表面上的第一导热层。 半导体管芯的第二表面安装到牺牲载体上。 密封剂沉积在第一导热层和牺牲载体上。 将密封剂平坦化以暴露第一导热层。 第一绝缘层形成在半导体管芯的第二表面和密封剂的第一表面上。 半导体管芯的第二表面上的第一绝缘层的一部分被去除。 在第一绝缘层的去除部分内的半导体管芯的第二表面上形成第二导热层。 在第二导热层周围的绝缘层内形成导电层。 散热器可以安装在第一导热层上。

公开(公告)号：US20150145128A1

公开(公告)日：2015-05-28

申请号：US14612075

申请日：2015-02-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/538 ,  H01L25/07 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.

Abstract translation: 半导体器件包括第一半导体管芯。 密封剂围绕第一半导体管芯设置。 第一阶梯式互连结构设置在密封剂的第一表面上。 在第一阶梯式互连结构中形成开口。 第一级互连结构中的开口在第一半导体管芯之上。 第二半导体管芯设置在第一阶梯式互连结构的开口中。 第二阶梯互连结构设置在第一阶梯式互连结构之上。 通过密封剂形成导电柱。

公开(公告)号：US08791556B2

公开(公告)日：2014-07-29

申请号：US13791375

申请日：2013-03-08

Applicant: STATS ChipPAC Ltd.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：电端子; 在电气端子周围的电路保护材料，并形成为具有凹陷垫体积; 电路保护材料顶表面上的可路由电路; 以及与电端子电连接的集成电路管芯。

公开(公告)号：US20140197540A1

公开(公告)日：2014-07-17

申请号：US14214120

申请日：2014-03-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan

IPC: H01L23/00

CPC classification number: H01L24/97 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract translation: 半导体器件首先通过锯切街道引导件提供晶片，并且具有形成在晶片的有效表面上的接合焊盘。 晶片用切割胶带胶带。 将晶片沿着锯条导轨分割为具有在多个模具中的每一个之间具有多个间隙的多个模具。 切割带被拉伸以将多个间隙扩展到预定距离。 有机材料沉积在多个间隙中的每一个中。 有机材料的顶表面与多个管芯的第一管芯的顶表面基本共面。 重分布层在有机材料的一部分上被图案化。 凹凸金属化（UBM）通过再分配层与接合焊盘电连接在有机材料上沉积。