公开(公告)号：US11557364B1

公开(公告)日：2023-01-17

申请号：US17443556

申请日：2021-07-27

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Balwinder Singh Soni ,  Avneep Kumar Goyal

IPC: G11C29/38 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C29/12 ,  H03K19/20

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

公开(公告)号：US10924091B2

公开(公告)日：2021-02-16

申请号：US16460191

申请日：2019-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: H03K3/037 ,  H03K19/21 ,  H03L7/00

Abstract: A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

公开(公告)号：US12210609B2

公开(公告)日：2025-01-28

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/85 ,  G06F11/362 ,  G06F21/31 ,  G06F21/44 ,  G06F21/45 ,  G06F21/71

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

公开(公告)号：US20240311227A1

公开(公告)日：2024-09-19

申请号：US18122420

申请日：2023-03-16

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F11/07 ,  G06F1/08

CPC classification number: G06F11/0793 ,  G06F1/08 ,  G06F11/0745

Abstract: According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.

公开(公告)号：US11687428B2

公开(公告)日：2023-06-27

申请号：US17152901

申请日：2021-01-20

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: G06F11/00 ,  G06F11/263 ,  G06F1/06 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F1/06 ,  G06F11/2236

Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

公开(公告)号：US20220229752A1

公开(公告)日：2022-07-21

申请号：US17152901

申请日：2021-01-20

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal

IPC: G06F11/263 ,  G06F11/22 ,  G06F1/06

Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

公开(公告)号：US11360143B2

公开(公告)日：2022-06-14

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar Goyal ,  Deepak Baranwal ,  Thomas Szurmant ,  Nicolas Bernard Grossier

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F11/34 ,  G01R31/319 ,  G06F11/36

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.