公开(公告)号：US10346097B2

公开(公告)日：2019-07-09

申请号：US15360661

申请日：2016-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Suk Kim ,  Jung-Yun Yun ,  Bongsoon Lim

IPC: G11C16/04 ,  G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory device and a controller configured to send first data, an address, and a first command to the nonvolatile memory device. The controller also sends at least one data to the nonvolatile memory device after sending the first command. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the first command. When receiving the at least one data from the controller, the nonvolatile memory device is configured to continue to perform the program operation based on the first data and the at least one data.

公开(公告)号：US20240233857A1

公开(公告)日：2024-07-11

申请号：US18395010

申请日：2023-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihan Ko ,  Sang-Won Park ,  Won-Taeck Jung ,  Heewon Son ,  Bongsoon Lim

IPC: G11C29/56

CPC classification number: G11C29/56004 ,  G11C29/56012 ,  G11C29/56016 ,  G11C2029/5602

Abstract: A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.

公开(公告)号：US11942154B2

公开(公告)日：2024-03-26

申请号：US17825764

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsoo Jeon ,  Bongsoon Lim ,  Sangwan Nam

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/08 ,  G11C16/20

CPC classification number: G11C16/0433 ,  G11C5/063 ,  G11C16/08 ,  G11C16/20

Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

公开(公告)号：US11830805B2

公开(公告)日：2023-11-28

申请号：US17212222

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongha Shin ,  Jeawon Jeong ,  Bongsoon Lim

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

公开(公告)号：US11830558B2

公开(公告)日：2023-11-28

申请号：US17742142

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Shim ,  Sangwon Park ,  Bongsoon Lim ,  Yoonhee Choi

IPC: G11C16/30 ,  G11C5/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/30 ,  G11C5/14 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

公开(公告)号：US20230013747A1

公开(公告)日：2023-01-19

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11515325B2

公开(公告)日：2022-11-29

申请号：US17025479

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11556 ,  H01L27/11526 ,  G11C8/14 ,  H01L27/11519

Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

公开(公告)号：US11501847B2

公开(公告)日：2022-11-15

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C29/00 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11467932B2

公开(公告)日：2022-10-11

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11355205B2

公开(公告)日：2022-06-07

申请号：US17172288

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Shim ,  Sangwon Park ,  Bongsoon Lim ,  Yoonhee Choi

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C5/14

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.