公开(公告)号：US11798629B2

公开(公告)日：2023-10-24

申请号：US17489988

申请日：2021-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C7/14 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/349 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11367735B2

公开(公告)日：2022-06-21

申请号：US16835484

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Daeseok Byeon

IPC: H01L27/11575 ,  H01L27/11551 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/04 ,  H01L27/11519 ,  H01L27/11548

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

公开(公告)号：US11200002B2

公开(公告)日：2021-12-14

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US11062775B2

公开(公告)日：2021-07-13

申请号：US16846539

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoon Lim ,  Jung-Yun Yun ,  Ji-Suk Kim ,  Sang-Won Park

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

公开(公告)号：US11709629B2

公开(公告)日：2023-07-25

申请号：US17455037

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US11495541B2

公开(公告)日：2022-11-08

申请号：US16592886

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

IPC: H01L23/535 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

公开(公告)号：US11043274B2

公开(公告)日：2021-06-22

申请号：US16851622

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C7/10 ,  G11C7/22 ,  G11C16/26

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

公开(公告)号：US20210149598A1

公开(公告)日：2021-05-20

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US10796767B2

公开(公告)日：2020-10-06

申请号：US16199098

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Minsu Kim ,  Hyun-Wook Park ,  Bongsoon Lim

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/04

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.

公开(公告)号：US20190333586A1

公开(公告)日：2019-10-31

申请号：US16163968

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Jin-Young Kim ,  Kuihan Ko ,  Han Il Park ,  Bongsoon Lim

IPC: G11C16/14 ,  G06F3/06

Abstract: A storage device includes a nonvolatile memory device that includes memory blocks, each including memory cells, and a controller that receives a first write request from an external host device. Depending on the first write request, the controller transmits a first sanitize command to the nonvolatile memory device and transmits first write data and a first write command associated with the first write request to the nonvolatile memory device. The nonvolatile memory device is configured to sanitize first data previously written to first memory cells of a first memory block of the memory blocks in response to the first sanitize command. The nonvolatile memory device is further configured to write the first write data to second memory cells of the first memory block in response to the first write command.