公开(公告)号：US11996358B2

公开(公告)日：2024-05-28

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Jeonggi Jin ,  Jinho Chun

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20230089399A1

公开(公告)日：2023-03-23

申请号：US17719721

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Solji SONG ,  Junyun Kweon ,  Jumyong Park ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/78 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/16

Abstract: A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.

公开(公告)号：US20210343634A1

公开(公告)日：2021-11-04

申请号：US17099929

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il CHOI ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

公开(公告)号：US12199056B2

公开(公告)日：2025-01-14

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Unbyoung Kang ,  Byeongchan Kim ,  Solji Song ,  Chungsun Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20240213109A1

公开(公告)日：2024-06-27

申请号：US18371714

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Chungsun Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L23/3178 ,  H01L23/291 ,  H01L24/08 ,  H01L24/16 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2924/1435 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first semiconductor device including a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a trench extending into the first interconnect structure and a portion of the first semiconductor substrate, a second semiconductor device on the first semiconductor device, and a cover insulating layer on the first semiconductor device and a side surface of the second semiconductor device, the cover insulating layer including a first portion filling the trench included in the first semiconductor device and contacting the first semiconductor substrate.

公开(公告)号：US12014977B2

公开(公告)日：2024-06-18

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Seok Hong ,  Dongwoo Kim ,  Hyunah Kim ,  Un-Byoung Kang ,  Chungsun Lee

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20240088092A1

公开(公告)日：2024-03-14

申请号：US18462610

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Woohyeong Kim ,  Jinwoo Park ,  Jayeon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.

公开(公告)号：US11923309B2

公开(公告)日：2024-03-05

申请号：US17210044

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-Il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US11854893B2

公开(公告)日：2023-12-26

申请号：US17850714

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/0206 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97

Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

公开(公告)号：US11705323B2

公开(公告)日：2023-07-18

申请号：US17078278

申请日：2020-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungseok Ahn ,  Unbyoung Kang ,  Chungsun Lee ,  Teakhoon Lee

IPC: H01L21/02 ,  H01L21/304 ,  B24B21/00 ,  B28D5/02 ,  B26D7/18 ,  H01L21/68

CPC classification number: H01L21/02021 ,  B24B21/002 ,  B26D7/18 ,  B28D5/02 ,  H01L21/304 ,  H01L21/68

Abstract: The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.