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    MOLDING APPARATUS OF SEMICONDUCTOR PACKAGE
    6.
    发明公开
    MOLDING APPARATUS OF SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230395403A1

    公开(公告)日：2023-12-07

    申请号：US18134718

    申请日：2023-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Park ,  Myungsung Kang ,  Jaekyung Yoo ,  Unbyoung Kang ,  Chungsun Lee

    IPC: H01L21/67

    CPC classification number: H01L21/67126

    Abstract: A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.

    Wafer structure and semiconductor device
    8.
    发明授权
    Wafer structure and semiconductor device 有权

    公开(公告)号：US12224256B2

    公开(公告)日：2025-02-11

    申请号：US17711370

    申请日：2022-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

    Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

    Semiconductor package
    9.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12218102B2

    公开(公告)日：2025-02-04

    申请号：US17728727

    申请日：2022-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngkun Jee ,  Unbyoung Kang ,  Sanghoon Lee ,  Chungsun Lee

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

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