Abstract:
In order to solve a problem in which when a terminal is converted from an active state of transmitting data to an inactive state, the transmission power of the terminal rapidly increases, a base station can control the transmission power by predicting and reflecting, in a target SIR, a decrease in SIR which results from an increase in interference amount due to data transmission of another terminal. The present invention can ensure the quality of an uplink control channel by controlling power in consideration of the effect of interference, even when the terminal is in an inactive state.
Abstract:
Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.
Abstract:
A semiconductor device including a substrate including a cell array region and a peripheral circuit region, the substrate including first active region defined in the cell array region and second active region defined in the peripheral circuit region, a plurality of word lines in the substrate and extending in a first direction, a bit line in the cell array region and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on corresponding once of the word lines, respectively, and extending in the first direction, a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns, and a second pad separation pattern between two adjacent ones of the first pad separation patterns and being adjacent to the cell pad structure may be provided.
Abstract:
A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.
Abstract:
A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.
Abstract:
A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.