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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210408008A1

    公开(公告)日：2021-12-30

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/24

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210057416A1

    公开(公告)日：2021-02-25

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR DEVICE HAVING SUPPORTERS AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SUPPORTERS AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有支持者的半导体器件及其制造方法

    公开(公告)号：US20170077102A1

    公开(公告)日：2017-03-16

    申请号：US15083819

    申请日：2016-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/45 ,  H01L23/522

    CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

    Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

    Abstract translation: 半导体器件包括衬底上的存储电极和被配置为耦合存储电极的一个或多个部分的一个或多个支撑器。 半导体器件可以包括平行于衬底的表面延伸的多个不相交的支撑体。 至少一个支撑件可以具有与存储电极的上表面基本上共面的上表面。 存储电极可以包括保形地覆盖存储电极的一个或多个表面和一个或多个支持者的电容器电介质层。 存储电极可以包括耦合在一起的上部和下部存储电极。 上下存储电极可以具有不同的水平宽度。

    METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING EDGE CHIP AND RELATED DEVICE
    8.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING EDGE CHIP AND RELATED DEVICE 有权
    形成包括边缘芯片的半导体器件的方法和相关器件

    公开(公告)号：US20170069633A1

    公开(公告)日：2017-03-09

    申请号：US15148405

    申请日：2016-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

    IPC: H01L27/108 ,  H01L21/027 ,  H01L49/02 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/311

    CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

    Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

    Abstract translation: 一种形成半导体器件的方法包括在包括蚀刻停止层的基底上形成模制层和支撑层，在支撑层上形成掩模层，在掩模层上形成第一边缘阻挡层，通过 蚀刻掩模层，形成孔，在孔中形成下电极，在载体层上形成支持体掩模层，在载体掩模层上形成第二边缘阻挡层，通过图案化载体掩模层形成载体掩模图案 形成穿过支撑层的支撑件开口，去除模制层，在下电极上形成电容器电介质层和上电极，在上电极上形成层间绝缘层，并平坦化层间绝缘层。 孔穿过支撑层，模制层和蚀刻停止层。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220115382A1

    公开(公告)日：2022-04-14

    申请号：US17555829

    申请日：2021-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjun LEE ,  Sang Chul SHIN ,  Bong-Soo KIM ,  Jiyoung KIM

    IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528

    Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200111793A1

    公开(公告)日：2020-04-09

    申请号：US16707019

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

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