公开(公告)号：US09241407B2

公开(公告)日：2016-01-19

申请号：US13747832

申请日：2013-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H05K3/00 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract translation: 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。

公开(公告)号：US20150060931A1

公开(公告)日：2015-03-05

申请号：US14327138

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Min Jung ,  Jeong-Kyu Ha

IPC: H01L23/14 ,  H01L23/538 ,  H01L27/15

CPC classification number: H01L27/15 ,  H01L23/145 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2924/014

Abstract: Semiconductor packages are provided. A semiconductor package may include a semiconductor chip. The semiconductor package may include a substrate and first and second conductive regions on the substrate. In some embodiments, the substrate may be a flexible substrate, and the first and second conductive regions may be on the same surface of the flexible substrate. Display devices including semiconductor packages are also provided. In some embodiments, a display device may include a flexible substrate that is bent such that first and second conductive regions thereof are connected to each other via an intervening third conductive region.

Abstract translation: 提供半导体封装。 半导体封装可以包括半导体芯片。 半导体封装可以包括衬底和衬底上的第一和第二导电区域。 在一些实施例中，衬底可以是柔性衬底，并且第一和第二导电区域可以在柔性衬底的相同表面上。 还提供了包括半导体封装的显示装置。 在一些实施例中，显示装置可以包括弯曲的柔性基板，使得其第一和第二导电区域经由居间的第三导电区域相互连接。

公开(公告)号：US20130240917A1

公开(公告)日：2013-09-19

申请号：US13780648

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong soon Cho ,  KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/525 ,  H02H9/04

CPC classification number: H01L23/5256 ,  H01L23/4985 ,  H01L23/60 ,  H01L2924/0002 ,  H02H9/041 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug.

Abstract translation: 提供半导体封装。 半导体封装可以包括具有第一表面和与第一表面相对的第二表面的基膜，在基膜的第一表面上的互连图案和基膜的第二表面上的接地层。 所述半导体封装还可以包括在所述第一区域内的所述基膜的第一表面上的半导体芯片和穿过所述基膜的所述第二区域中的通孔接触插塞，并且被配置为当静电时将所述互连图案与所述接地层电连接 通过通孔接触插头发生放电。

公开(公告)号：US12243798B2

公开(公告)日：2025-03-04

申请号：US17729734

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Min Jung

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a circuit substrate, a semiconductor chip mounted on the circuit substrate, and a thermal radiation film covering the semiconductor chip on the circuit substrate. The semiconductor chip includes first lateral surfaces opposite to each other in a first direction and second lateral surfaces opposite to each other in a second direction that intersects the first direction. A first width of the first lateral surface is less than a second width of the second lateral surface. The thermal radiation film covers a top surface of the semiconductor chip and entirely surrounds the first and second lateral surfaces of the semiconductor chip. The thermal radiation film has slits directed toward the first lateral surfaces from ends of the thermal radiation film.

公开(公告)号：US20240079311A1

公开(公告)日：2024-03-07

申请号：US18229035

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO.,LTD

Inventor： Seung Hyun CHO ,  Jeong-Kyu Ha ,  Jae-Min Jung

IPC: H01L23/498 ,  B32B7/12 ,  B32B27/06

CPC classification number: H01L23/4985 ,  B32B7/12 ,  B32B27/06 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.

公开(公告)号：US09280182B2

公开(公告)日：2016-03-08

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L29/18 ,  G06F1/16 ,  G06F3/041 ,  H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。

公开(公告)号：US09059162B2

公开(公告)日：2015-06-16

申请号：US13933185

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.

Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。

公开(公告)号：US20140246687A1

公开(公告)日：2014-09-04

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。

公开(公告)号：US12191246B2

公开(公告)日：2025-01-07

申请号：US18505613

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/498 ,  H01L23/00

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

公开(公告)号：US11764140B2

公开(公告)日：2023-09-19

申请号：US17391164

申请日：2021-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk Han ,  Duck Gyu Kim ,  Min Ki Kim ,  Jae-Min Jung ,  Jeong-Kyu Ha

IPC: H01L23/58 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/585

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.