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    SEMICONDUCTOR PACKAGE INCLUDING INSULATING MATERIAL
    11.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING INSULATING MATERIAL 有权

    公开(公告)号：US20250105133A1

    公开(公告)日：2025-03-27

    申请号：US18828196

    申请日：2024-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung KIM ,  Okseon YOON ,  Jiyoung YOON ,  Kiseok KIM ,  Jihye SHIM

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/03

    Abstract: A semiconductor package includes a redistribution structure including a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer, a semiconductor chip mounted on the redistribution structure and including connection pads, internal connection terminals between the redistribution structure and the semiconductor chip electrically connecting the redistribution layer to the connection pads, external connection terminals attached under the redistribution structure and electrically connected to the redistribution layer, and an encapsulant configured to surround the semiconductor chip and the internal connection terminals on the redistribution structure. The insulating layer includes an insulating material of which K is 20 to 100 in a TC index according to equation below. K = U T ( α 1 - α 2 ) × Δ ⁢ T × E [ TC ⁢ INDEX ]

    IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
    12.
    发明申请
    IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230082070A1

    公开(公告)日：2023-03-16

    申请号：US17744045

    申请日：2022-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyeongjae BYEON ,  Jinyoung KIM ,  Seungjoo NAH ,  Heegeun JEONG

    IPC: H01L27/146

    Abstract: An image sensor includes a substrate including a first region and a second region surrounding the first region, a light sensing element in the substrate, a planarization layer on the light sensing element, a color filter array layer including color filters on the planarization layer on the first region of the substrate, a light blocking metal pattern on the planarization layer on the second region of the substrate, a dummy color filter layer on the light blocking metal pattern on a portion of the second region adjacent to the first region of the substrate, and microlens on the color filter array layer. Active pixels are in the first region, and optical black (OB) pixels are in the second region.

    3D MEMORY DEVICE
    13.
    发明申请
    3D MEMORY DEVICE 有权

    公开(公告)号：US20220215879A1

    公开(公告)日：2022-07-07

    申请号：US17705613

    申请日：2022-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Makoto HIRANO ,  Jinyoung KIM

    IPC: G11C13/00

    Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.

    MEMORY DEVICE
    14.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240282387A1

    公开(公告)日：2024-08-22

    申请号：US18509250

    申请日：2023-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunhyang PARK ,  Jinyoung KIM ,  Sehwan PARK

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

    Abstract: A memory device includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which a row decoder is connected to the plurality of memory cells through a plurality of wordlines, a plurality of page buffers connected to the plurality of memory cells through a plurality of bitlines, and a control logic controlling the row decoder and the plurality of page buffers are arranged. The row decoder inputs a plurality of read voltages having different levels to a selected wordline among the plurality of wordlines in sequence. Each of the plurality of page buffers includes a sensing node connected to one of the plurality of bitlines. Voltages of the sensing nodes included in the page buffers of a portion of the plurality of page buffers decrease differently while each of the plurality of read voltages is input to the selected wordline.

    OPERATING METHOD OF A NONVOLATILE MEMORY DEVICE FOR PROGRAMMING MULTI-PAGE DATA
    16.
    发明申请
    OPERATING METHOD OF A NONVOLATILE MEMORY DEVICE FOR PROGRAMMING MULTI-PAGE DATA 有权

    公开(公告)号：US20230044730A1

    公开(公告)日：2023-02-09

    申请号：US17968912

    申请日：2022-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wandong KIM ,  Jinyoung KIM ,  Sehwan PARK ,  Hyun Seo ,  Sangwan NAM

    IPC: G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

    IMAGE SENSOR
    17.
    发明申请
    IMAGE SENSOR 有权

    公开(公告)号：US20220271077A1

    公开(公告)日：2022-08-25

    申请号：US17668524

    申请日：2022-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongchul LEE ,  Jinyoung KIM ,  Beomsuk LEE ,  Kwansik CHO ,  Hochul JI

    IPC: H01L27/146

    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface. The first surface includes an element isolation trench. An element isolation layer is arranged inside the element isolation trench. The element isolation layer defines an active region. A gate electrode is arranged on the first surface of the semiconductor substrate. An interlayer insulating layer is arranged on the first surface of the semiconductor substrate and covers the gate electrode. A ground contact is configured to penetrate the element isolation layer and the interlayer insulating layer and contacts the semiconductor substrate. A color filter is arranged on the second surface of the semiconductor substrate.

    NON-VOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND READING METHOD THEREOF
    19.
    发明申请
    NON-VOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND READING METHOD THEREOF 有权

    公开(公告)号：US20220222139A1

    公开(公告)日：2022-07-14

    申请号：US17399528

    申请日：2021-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongmin SHIN ,  Jinyoung KIM ,  Sehwan PARK ,  Youngdeok SEO

    IPC: G06F11/10 ,  H03M13/45

    Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

    CONTROLLER, A STORAGE DEVICE INCLUDING THE CONTROLLER, AND A READING METHOD OF THE STORAGE DEVICE
    20.
    发明申请
    CONTROLLER, A STORAGE DEVICE INCLUDING THE CONTROLLER, AND A READING METHOD OF THE STORAGE DEVICE 有权

    公开(公告)号：US20220005539A1

    公开(公告)日：2022-01-06

    申请号：US17156801

    申请日：2021-01-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK ,  Sangwan NAM

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18

    Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

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