MEMORY DEVICE AND METHOD OF OPERATING THE SAME

    公开(公告)号:US20240221843A1

    公开(公告)日:2024-07-04

    申请号:US18470931

    申请日:2023-09-20

    CPC classification number: G11C16/26 G11C16/0433 G11C16/08

    Abstract: Disclosed is a method of operating a memory device including a memory cell array. The memory cell array includes a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells. The method includes performing an additional read operation on the plurality of memory cells by adjusting a voltage level applied to a selected word line WLN connected to memory cells to be additionally read for improvements in memory cell sensing characteristics and a voltage level applied to a plurality of unselected word lines WLUnselect, and performing a main read operation on the plurality of memory cells by adjusting a voltage level applied to at least one first word line among the plurality of unselected word lines WLUnselect to be different from a voltage level applied to the at least one first word line in the additional read operation.

    NONVOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND READING METHOD OF STORAGE DEVICE INCLUDING THE SAME

    公开(公告)号:US20220276802A1

    公开(公告)日:2022-09-01

    申请号:US17522578

    申请日:2021-11-09

    Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.

    METHOD AND APPARATUS FOR PROVIDING SEARCH FUNCTION IN TOUCH-SENSITIVE DEVICE

    公开(公告)号:US20230027759A1

    公开(公告)日:2023-01-26

    申请号:US17955992

    申请日:2022-09-29

    Inventor: Sehwan PARK

    Abstract: A method and an apparatus are provided for executing applications. Based on a first user input, a first window including number keys is displayed. Based on a second user input selecting a key, a second window is displayed including a list of applications. Based on an application being selected, the selected application is mapped to the selected key and an icon image corresponding to the selected application is displayed in the selected key. After the selected application is mapped, a third user input is received corresponding to the selected key. In response to the third user input, a function is performed associated with the selected application in case that a duration of the third user input is longer than or equal to a threshold duration, and an operation different from the function is performed in case that the duration is shorter than the threshold duration.

    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES

    公开(公告)号:US20220254433A1

    公开(公告)日:2022-08-11

    申请号:US17469422

    申请日:2021-09-08

    Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

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