中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.023 seconds)

    SEMICONDUCTOR MEMORY DEVICES
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200111793A1

    公开(公告)日：2020-04-09

    申请号：US16707019

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
    具有盖式结构的半导体器件及其制造方法

    公开(公告)号：US20160240619A1

    公开(公告)日：2016-08-18

    申请号：US15011820

    申请日：2016-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

    IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

    CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

    Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

    SEMICONDUCTOR DEVICE
    14.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230170891A1

    公开(公告)日：2023-06-01

    申请号：US18051138

    申请日：2022-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonju LEE ,  Jiyoung KIM ,  Jaehyun PARK ,  Seuk SON ,  Sooeun LEE ,  Dongchul CHOI

    IPC: H03K5/26 ,  H03K3/037

    CPC classification number: H03K5/26 ,  H03K3/037 ,  H03K2005/00286

    Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

    TRANSMITTER AND RECEIVER FOR LOW POWER INPUT/OUTPUT AND MEMORY SYSTEM INCLUDING THE SAME
    16.
    发明申请
    TRANSMITTER AND RECEIVER FOR LOW POWER INPUT/OUTPUT AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220069822A1

    公开(公告)日：2022-03-03

    申请号：US17353917

    申请日：2021-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byongmo MOON ,  Jiyoung KIM ,  Seongook JUNG ,  Jongsoo LEE

    IPC: H03K19/173 ,  H03K19/0175 ,  H03K19/017 ,  H03K19/17788 ,  G11C7/14 ,  G11C7/22

    Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

    SEMICONDUCTOR MEMORY DEVICES
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210057416A1

    公开(公告)日：2021-02-25

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    18.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200144380A1

    公开(公告)日：2020-05-07

    申请号：US16445815

    申请日：2019-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Joon-Sung LIM ,  Jiyoung KIM ,  Jiwon KIM ,  Woosung YANG

    IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.

Patent Agency Ranking