公开(公告)号：US20220375959A1

公开(公告)日：2022-11-24

申请号：US17552812

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Jiwon KIM ,  Sung-Min HWANG ,  Sukkang SUNG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

公开(公告)号：US20250072001A1

公开(公告)日：2025-02-27

申请号：US18800667

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeol LEE ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes: a peripheral circuit structure including a substrate and a circuit that is disposed on the substrate; a cell structure disposed on the peripheral circuit structure and including gate electrodes and a channel that extends through the gate electrodes; and a bonding structure located between the peripheral circuit structure and the cell structure, wherein the bonding structure includes: a first insulating layer attached to the peripheral circuit structure; a first bonding pad disposed on the peripheral circuit structure and electrically connected to the circuit; a second insulating layer attached to the cell structure; a second bonding pad disposed on the cell structure and electrically connected to the gate electrodes; and an anisotropic conductive adhesive layer located between the first insulating layer and the second insulating layer and between the first bonding pad and the second bonding pad, and including a plurality of conductive particles.

公开(公告)号：US20240203875A1

公开(公告)日：2024-06-20

申请号：US18239504

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon KIM ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions and including a plate layer; gate electrodes spaced apart from each other in a first direction; channel structures passing through the gate electrodes; gate separation regions extending in a second direction; first and second upper isolation regions dividing an upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions; and contact plugs extending in the first direction, each of the first and second upper isolation regions has a region extending in a third direction, and the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, and the first sub-gate electrode is connected to one of the contact plugs.

公开(公告)号：US20240114704A1

公开(公告)日：2024-04-04

申请号：US18187803

申请日：2023-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung KWON ,  Jiyoung KIM ,  Woosung YANG ,  Sukkang SUNG

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include a first substrate, a peripheral circuit structure on the first substrate, the peripheral circuit structure including first bonding pads in an upper portion of the peripheral circuit structure, and a cell array structure on the peripheral circuit structure. The cell array structure may include a second substrate, a stack interposed between the peripheral circuit structure and the second substrate, a first insulating layer enclosing the stack, a dummy plug penetrating the first insulating layer, a second insulating layer on the dummy plug, and second bonding pads interposed between the stack and the peripheral circuit structure and connected to the dummy plug. The first bonding pads may contact the second bonding pads, and the dummy plug may be electrically connected to the first bonding pads and the second bonding pads. A top surface of the dummy plug may contact the second insulating layer.

公开(公告)号：US20230005947A1

公开(公告)日：2023-01-05

申请号：US17715508

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemin YOO ,  Woosung YANG ,  Sukkang SUNG ,  Ahreum LEE

IPC: H01L27/11573 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11582

Abstract: A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.

公开(公告)号：US20220139855A1

公开(公告)日：2022-05-05

申请号：US17328176

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joon-Sung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/10

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US20220102334A1

公开(公告)日：2022-03-31

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon KIM ,  Jaeho AHN ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

公开(公告)号：US20250167115A1

公开(公告)日：2025-05-22

申请号：US18925771

申请日：2024-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo GU ,  Bumkyu KANG ,  Ahreum LEE ,  Junhyoung KIM ,  Jiwon KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B12/00 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.

公开(公告)号：US20250087584A1

公开(公告)日：2025-03-13

申请号：US18666962

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyung KIM ,  Chulhae PARK ,  Younghwan SON ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor structure including, circuit devices on a substrate, a lower interconnection structure, and a capacitor structure on a same level as a level of at least a portion of the lower interconnection structure, and a second semiconductor structure on the first semiconductor structure and including a plurality of memory cells arranged three-dimensionally. The lower interconnection structure includes a lower contact, a lower line on the lower contact, an upper contact on the lower line, and an upper line on the upper contact. The capacitor structure includes first electrode structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, second electrode structures positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and dielectric layers between the first electrode structures and the second electrode structures.

公开(公告)号：US20250081457A1

公开(公告)日：2025-03-06

申请号：US18426564

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyoon YEO ,  Joonsung KIM ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a gate stack including conductive patterns and interlayer insulating patterns, which are alternately stacked with each other, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure. The memory layer and the source structure are spaced apart from each other, and the insulating pattern is in contact with the channel layer, the memory layer, and the source structure.