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    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230054984A1

    公开(公告)日：2023-02-23

    申请号：US17722616

    申请日：2022-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsung KIM

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250069979A1

    公开(公告)日：2025-02-27

    申请号：US18943337

    申请日：2024-11-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eunseok CHO ,  Minjeong GU ,  Joonsung KIM ,  Jaehoon CHOI

    IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

    Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

    SEMICONDUCTOR PACKAGE
    6.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240038642A1

    公开(公告)日：2024-02-01

    申请号：US18121429

    申请日：2023-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongkyu Kim ,  Joonsung KIM ,  Hyeonseok LEE ,  Hyeonjeong HWANG

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

    CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

    Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230012115A1

    公开(公告)日：2023-01-12

    申请号：US17570874

    申请日：2022-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220068730A1

    公开(公告)日：2022-03-03

    申请号：US17196538

    申请日：2021-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsung KIM ,  Yonghwan KWON ,  Sanguk KIM

    IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

    FAN-OUT SEMICONDUCTOR PACKAGE
    9.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210384095A1

    公开(公告)日：2021-12-09

    申请号：US17409281

    申请日：2021-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonsung KIM ,  Doohwan Lee ,  Jinseon Park

    IPC: H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

    Abstract: A method of manufacturing a fan-out semiconductor package includes forming a frame having a through-hole and including one or more wiring layers; forming a semiconductor chip in the through-hole of the frame; forming an encapsulant covering an upper surface of each of the frame and the semiconductor chip, and filling a space between a wall surface of the through-hole of the frame and a side surface of the semiconductor chip; forming a connection structure below each of the frame and the semiconductor chip; forming a first metal pattern layer on an upper surface of the encapsulant; forming an insulating material on the upper surface of the encapsulant and covering the first metal pattern layer; and forming a second metal pattern layer on the insulating material, a first metal via passing through the insulating material, and a second metal via passing through the insulating material and the encapsulant.

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