NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

    公开(公告)号:US20230162807A1

    公开(公告)日:2023-05-25

    申请号:US17960346

    申请日:2022-10-05

    CPC classification number: G11C16/3427 G11C16/0483 G11C16/10 G11C16/3459

    Abstract: An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

    Electronic device and method for moving content display position on basis of coordinate information stored in display driver circuit

    公开(公告)号:US11373627B2

    公开(公告)日:2022-06-28

    申请号:US16956283

    申请日:2018-12-17

    Abstract: An electronic device according to various embodiments may comprise a display panel, a processor, and a display driver circuit including an internal memory and configured to drive the display panel, wherein the display driver circuit may be configured to: receive, from the processor, movement information of a designated content to be displayed on the display panel while the processor operates in a low power state; store the movement information in the internal memory; display the designated content at a first position on the display panel while the processor operates in the low power state; and move the designated content displayed at the first position to a second position on the display panel and display the same at the second position, at least on the basis of the movement information stored in the internal memory while the processor operates in the low power state.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20210066343A1

    公开(公告)日:2021-03-04

    申请号:US16847210

    申请日:2020-04-13

    Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

    Method and apparatus for multitasking

    公开(公告)号:US10168868B2

    公开(公告)日:2019-01-01

    申请号:US14167073

    申请日:2014-01-29

    Abstract: A method for multitasking in an electronic device is provided, the method including: displaying a first one of a plurality of function execution screens as a top layer screen on a display unit of the electronic device; receiving, by the electronic device, a first touch input; and displaying, in response to the first touch input, a first layer separation object for causing a second one of the plurality of function execution screens to be at least partially displayed as the top layer screen on the display unit; wherein the first layer separation object is displayed concurrently with the first function execution screen.

    Method and apparatus for operating electronic device

    公开(公告)号:US10089380B2

    公开(公告)日:2018-10-02

    申请号:US14584022

    申请日:2014-12-29

    Abstract: A method is provided comprising: generating, by an electronic device, at least one context information log associated with content stored in a memory; grouping the content into a plurality of groups based on the at least one context information log; adding the plurality of groups to a first list, wherein each of the plurality of groups is associated with a respective time-out period; generating a first screen based on the first list, the first screen including a first group from the plurality; detecting an input to the first screen that selects the first group and in response, adding the first group to a second list; wherein the first group is removed from the first list when the respective time-out period of the first group expires, and the first group persists in the second list after the respective time-out period of the first group expires.

    Operation method of memory device and operation method of memory system including the same

    公开(公告)号:US12176046B2

    公开(公告)日:2024-12-24

    申请号:US17955858

    申请日:2022-09-29

    Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

    Flash memory device having multi-stack structure and channel separation method thereof

    公开(公告)号:US12119066B2

    公开(公告)日:2024-10-15

    申请号:US17982081

    申请日:2022-11-07

    CPC classification number: G11C16/102 G11C16/08 G11C16/12

    Abstract: A flash memory device is provided. The flash memory device includes: a first memory cell; a second memory cell on the first memory cell; and a third memory cell between the first memory cell and the second memory cell. The first memory cell, the second memory cell and the third memory cell share a channel. The third memory cell is configured to block channel sharing between the first memory cell and the second memory cell based on a channel separation voltage provided in first to k-th program loops. The third memory cell is configured to connect the channel sharing between the first memory cell and the second memory cell based on a channel connection voltage provided to the third memory cell in a (k+1)-th program loop.

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