Abstract:
A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.
Abstract:
An electronic device is provided. The electronic device includes a housing, a display rollable into the housing, and a display driver circuitry operably coupled to the display. The display driver circuitry is configured to display, while the electronic device is in a first state in which a first display area of the display is exposed and a second display area of the display adjacent to the first display area is rolled into the housing, a first image in the exposed first display area, obtain, a second image based on applying a first weight to a pixel value of a first pixel of a first horizontal line and applying a second weight less than the first weight to a pixel value of a second pixel of the first horizontal line, and display, while displaying the first image, the second image in the second display area rolled into the housing.
Abstract:
A flash memory device is provided. The flash memory device includes: a first memory cell; a second memory cell on the first memory cell; and a third memory cell between the first memory cell and the second memory cell. The first memory cell, the second memory cell and the third memory cell share a channel. The third memory cell is configured to block channel sharing between the first memory cell and the second memory cell based on a channel separation voltage provided in first to k-th program loops. The third memory cell is configured to connect the channel sharing between the first memory cell and the second memory cell based on a channel connection voltage provided to the third memory cell in a (k+1)-th program loop.
Abstract:
A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.
Abstract:
Disclosed is an electronic device comprising at least one sensor, a communication circuit, a display, and at least one processor operationally connected to the display, wherein the at least one processor is configured to: display, on the display, a watch screen including a fixed element displayed at a designated location on the display, a repetitive element displayed on the basis of at least a designated rule, and a changing element associated with information obtained through the at least one sensor or received through the communication circuit; generate first data on the basis of at least one of the designated rule or the shape of the repetitive element; generate second data based on at least one of the fixed element or the changing element, in response to the changing element changing from a first value to a second value; and generate first deterioration information on the basis of the first data, the second data, and the duration over which the changing element maintains the first value. Various other embodiments understood through the specification are also possible.
Abstract:
A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.
Abstract:
A lamp device for inputting or outputting a voice signal and a method of driving the same. The method of driving a lamp device includes receiving an audio signal; performing voice recognition of a first audio signal among the received audio signals; generating an activation signal based on the voice recognition result; transmitting the activation signal to the external device; receiving a first control signal from the external device; and transmitting a second audio signal among the received audio signals to the external device in response to the first control signal. Alternatively, various exemplary embodiment may be further included.
Abstract:
A method and an apparatus for controlling to lock or unlock in the portable terminal having a transparent display that has two display surfaces and is capable of double-sided touch input and double-sided display is provided. The method includes activating the transparent display according to a lock state or an unlock state of the transparent display; displaying a lock or unlock area, which notifies whether a display surface is locked, in a preset area of at least one of display surfaces of the transparent display; and changing the lock state or the unlock state of the at least one of the display surfaces of the transparent display and displaying whether the changed state is the lock state or the unlock state in the lock or unlock area of the at least one display surface, when a touch input is received in the lock or unlock area.
Abstract:
An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.
Abstract:
A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.